VC0736 datasheet(35/127 Pages) NEXTCHIP

35 / 127 page

NVP6124

Data sheet

02.11.2015 (REV 0.2)

33/125

4-CH AHD2.0 RX and 9-CH Audio Codec

3.3. Playback Output

Playback is to output stored audio data to external device through DAC after internal processing.

NVP6124 gives and takes a clock and synchronization signal through ACLK_PB and

ASYNC_PB pin. In this case, interface is the exactly same as Record data's interface. When

multi-channel audio is supported, selective playback for intended channel is enable using

In case of single channel, PB_SEL should be set

to "00000".

ACLK_PB and ASYNC_PB supports Master mode and Slave mode. In master mode, ACLK_PB

and ASYNC_PB are outputted by NVP6124, and clock and synchronization signal come from

external devices at slave mode. Master/Slave mode is selected by setting internal register

(PB_MASTER, 0x13[7], BANK1).

ADATA_PB accepts an audio data synchronized with ACLK_PB and ASYNC_PB. ACLK_PB

and ASYNCP accept I2S/DSP/SSP mode input and output, and I2S and DSP mode is set by

internal register value (PB_SYNC, 0x13[0], BANK1). When DSP mode is selected, DSP/SSP

mode is set by (PB_SSP, 0x13[1], BANK1). The relation of clock, synchronized signal and data

are the exactly same as that of record/mix output. PB_CLK can be inverted for all modes using

setting of register(PB_CLK, 0x13[6], BANK1).

3.4. Audio Detection

NVP6124 has an audio mute detection block for individual 9 channels. The mute detection

scheme uses absolute/differential amplitude detection method. The detection method and

accumulated period are defined by the ADET_MODE(0x29[3], BANK1) and ADET_FILT

(0x29[2:0], BANK1) register, and the detecting threshold values are defined by ADET_TH

Interrupt is generated through the interrupt pins.

VC0736 bảng dữ liệu(PDF) 35 Page - NEXTCHIP Co,Ltd