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VC0736 bảng dữ liệu(PDF) 25 Page - NEXTCHIP Co,Ltd

tên linh kiện VC0736
Giải thích chi tiết về linh kiện  4-CH AHD2.0 RX and 9-CH Audio Codec
PDF  127 Pages
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nhà sản xuất  NEXTCHIP [NEXTCHIP Co,Ltd]
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VC0736 bảng dữ liệu(HTML) 25 Page - NEXTCHIP Co,Ltd

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NVP6124
Data sheet
02.11.2015 (REV 0.2)
23/125
4-CH AHD2.0 RX and 9-CH Audio Codec
5. FPGA or equivalent devices which is input 148.5MHz time multiplexed data output, need to align
with same channel data(37.125MHz 1,2,3,4 channel). Figure2.16. shows how to use Channel ID as a
example.
odd field
even field
vertical active
vertical active
vertical blank
vertical blank
horizontal blank
horizontal active
FF
00
00
EAV
FF
00
00
SAV
CHID_TYPE
(0x54[2:0],BANK0 = 0x1)
0xD0
0xC0
CHID_VIN1 (0x55[3:0],BANK0 = 0x0)
FF
00
00
EAV
FF
00
00
SAV
0xD1
0xC1
CHID_VIN2 (0x55[7:4],BANK0 = 0x1)
FF
00
00
EAV
FF
00
00
SAV
0xD2
0xC2
CHID_VIN3 (0x56[3:0],BANK0 = 0x2)
FF
00
00
EAV
FF
00
00
SAV
0xD3
0xC3
CHID_VIN4 (0x56[7:4],BANK0 = 0x3)
CH4
CH1
CH2
00
CH4
CH1
CH2
00
CH4
CH1
CH2
D2
CH4
CH1
CH2
2
3
0
1
0
1
2
3
0
1
2
3
0
1
2
3
FF
00
00
D2
CH3
CH4
CH1
CH2
CH3
CH4
CH1
CH2
0
1
2
3
0
3
0
1
CH1
CH1
CH3
CH3
CH3
CH3
CH3
CH3
2
Counter
Change!!
CH4
CH4
CH4
CH4
CH2
CH2
CH1
CH1
CH1
CH1
CH3
CH3
CH2
CH2
CH2
CH2
CH4
CH4
Detect(ff,00,00) &
EAV/SAV check
Wrong sorting
Right sorting
1 CH : 37.125MHz output
NVP6124 : 148.5MHz output
NVP6124 : 148.5MHz clock
counter
CH3
CH4
CH1
CH2
CH1
3
0
1
1
F
V
H
CHID_VINx
7
6
5
4
3
2
1
0
EAV or SAV
2 CH : 37.125MHz output
3 CH : 37.125MHz output
4 CH : 37.125MHz output
Application
or FPGA, etc.
(0xC8[3:0],BANK1 = 0x8)
(0xCC[6:4],BANK1= 0x6)
FF
Figure 2.16. NVP6124 Select Channel ID
6. CHID_TYPE(BANK0, 0x54[2:0]=001) mode described in top of Figure2.16.
7. To generate 2bit digit, Design 2bit counter with VCLK1 (The 2bit digit means each channel).
8. Using 2bit digit, Convert from 148.5MHz Data to 37.125MHz Data (Wrong sorting part in Figure2.16.).
and then Define the 2bit digit ( 0 : 1ch data, 1 : 2ch data, 2 : 3ch data, 3 : 4ch data).
namely, 148.5MHz data output separate only with 37.125MHz, 4channel data, is not align with channel
data where becomes mapping in counter value.
9. For mapping between separated each channel data and specified counter value, Select channel
among separated each channel(1CH selected in Figure2.16.).
If selected channel data become Right sorting condition, other 3 channel is sorted automatically.
10. Check the 1ch data output when 2bit counter value is only '0' and then Search the EAV/SAV[3:0]
after FF 00 00 Code.
11. If the EAV/SAV[3:0] is '2', make a counter reset to '3' (Refer to Blue color in Figure2.16.)
12. Become Right sorting part.



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