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VC0736 bảng dữ liệu(PDF) 97 Page - NEXTCHIP Co,Ltd |
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VC0736 bảng dữ liệu(HTML) 97 Page - NEXTCHIP Co,Ltd |
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97 / 127 page  NVP6124 Data sheet 02.11.2015 (REV 0.2) 95/125 4-CH AHD2.0 RX and 9-CH Audio Codec Registers to Audio Interface ADDRESS REGISTER NAME BITS VALUE DESCRIPTION Bank Addr 30P 25P 1 0x06 CAS_PB [7] 0x1B 0x1B CAS_PB : The Usage of Playback Data when Cascade Mode 0 : use multiple playback data, received through all stage 1 : use single playback data, received through last stage TRANS_MODE [6] TRANS_MODE : Control the phase between transferred clock and cascade data 0 : Same phase 1 : Inverted phase CAS_PIN [4] CAS_PIN : Control the usage of ADATA_CASI and ADATA_CASO as cascade transmitting 0 : Don't Use 1 : Use CHIP_STAGE [1:0] CHIP_STAGE : Selection of chip state for cascade 0 : middle stage 2 : first stage 1 : last stage 3 : single chip operation 0x07 RM_MASTER [7] 0xC8 0xC8 RM_MASTER : Selection of master & slave mode of ACLK_REC and ASYNC_REC 0 : Slave mode operation 1 : Master mode operation RM_CLK [6] RM_CLK : Set the relationship between audio signal outputted to ADATA_REC and clock outputted to ACLK_REC 0 : inverted clock 1 : non-inverted clock RM_BITRATE [5:4] RM_BITRATE : Set the bit rate of audio signal outputted to ADATA_REC 0 : 256fs 2 : 320fs 1 : 384fs 3 : Don ’t Use RM_SAMRATE [3] RM_SAMRATE : Set the sampling rate of data outputted to ADATA_REC 0 : 8KHz 1 : 16KHz RM_BITWID [2] RM_BITWID : Set the bit width of data outputted to ADATA_REC 0 : 16bits 1 : 8bits RM_SSP [1] RM_SSP : Selection of DSP mode and SSP mode for ADATA_REC pin, when ASYNC_REC is DSP mode. 0 : DSP mode 1 : SSP mode RM_SYNC [0] RM_SYNC : Set the sync's mode inputted/outputted to ASYNC_REC. 0 : I2S mode 1 : DSP mode |
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