TAS5504_06 datasheet(80/96 Pages) TI

80 / 96 page

Serial Control Interface Register Definitions

SLES123 − October 2004

TAS5504

6.20 DRC1 Control (0x96, Channels 1−3)

Bits D31 – D14 are Don’t Care.

Table 6−22. DCR1 Control (0x96, Channels 1−3)

D31

D30

D29

D28

D27

D26

D25

D24

FUNCTION

Unused bits

D23

D22

D21

D20

D19

D18

D17

D16

FUNCTION

Unused bits

D15

D14

D13

D12

D11

D10

FUNCTION

−

Channel 1 (node j): No DRC

−

Channel 1 (node j): Pre-volume DRC

−

Channel 1 (node j): Post-volume DRC

−

Channel 1 (node j): No DRC

−

Channel 2 (node I): No DRC

−

Channel 2 (node I): Pre-volume DRC

−

Channel 2 (node I): Post-volume DRC

−

Channel 2 (node i): No DRC

FUNCTION

−

Channel 3 (node q): No DRC

−

Channel 3 (node q): Pre-volume DRC

−

Channel 3 (node q): Post-volume DRC

−

Channel 3 (node q): No DRC

6.21 DRC2 Control (0x97, Channel 4)

Table 6−23. DRC2 Control (0x97, Channel 4)

D31 – D2

FUNCTION

Channel 4 (node r): No DRC

Channel 4 (node r): Pre-volume DRC

Channel 4 (node r): Post-volume DRC

Channel 4 (node r): No DRC

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