TAS5504_06 datasheet(78/96 Pages) TI

78 / 96 page

Serial Control Interface Register Definitions

SLES123 − October 2004

TAS5504

6.16 Bass Management Registers (0x49–0x50)

Registers 0x49–0x50 provide configuration control for bass mangement.

Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as

a 32-bit word with the upper four bits not used.

Table 6−17. Bass Management Registers Format (0x49 – 0x50)

SUBADDRESS

TOTAL

BYTES

NAME

DESCRIPTION OF CONTENTS

DEFAULT STATE

0x49

ipmix_1_to_ch4

Input Mixer 1 to Ch 4 Mixer coefficient (default = 0)

U (31:28), ipmix14 (27:24), ipmix14 (23:16), ipmix14 (15:8),

ipmix14 (7:0)

0x00, 0x00, 0x00, 0x00

0x4A

ipmix_2_to_ch4

Input Mixer 2 to Ch 4 Mixer coefficient (default = 0)

U (31:28), ipmix24 (27:24), ipmix24 (23:16), ipmix24 (15:8),

ipmix24 (7:0)

0x00, 0x00, 0x00, 0x00

0x4B

ipmix_3_to_ch12 Input Mixer 3 to Ch 1 and Ch 2 Mixer coefficient (default = 0)

U (31:28), ipmix32 (27:24), ipmix32 (23:16), ipmix32 (15:8),

ipmix32 (7:0)

0x00, 0x00, 0x00, 0x00

0x4C

Ch3_bp_bq2

Ch 3 Biquad-2 By-pass coefficient (default = 0)

U (31:28), ch3_bp_bq2 (27:24), ch3_bp_bq2 (23:16),

ch3_bp_bq2 (15:8), ch3_bp_bq2 (7:0)

0x00, 0x00, 0x00, 0x00

0x4D

Ch3_bq2

Ch 3 Biquad-2 Inline coefficient (default = 1)

U (31:28), ch3_bq2 (27:24), ch3_bq2 (23:16), ch3_bq2 (15:8),

ch3_bq2 (7:0)

0x00, 0x80, 0x00, 0x00

0x4E

ipmix_4_to_ch12 Ch 4 Biquad-2 Output to Ch1 Mixer and Ch2 Mixer coefficient

(default = 0)

U (31:28), ipmix4_12 (27:24), ipmix4_12 (23:16), ipmix4_12

(15:8), ipmix4_12 (7:0)

0x00, 0x00, 0x00, 0x00

0x4F

Ch4_bp_bq2

Ch 4 Biquad-2 By-pass coefficient (default = 0)

0U (31:28), ch4_bp_bq2 (27:24), ch4_bp_bq2 (23:16),

ch4_bp_bq2 (15:8), ch4_bp_bq2 (7:0)

0x00, 0x00, 0x00, 0x00

0x50

Ch4_bq2

Ch 4 Biquad-2 Inline coefficient (default = 1)

U (31:28), ch4_bq2 (27:24), ch4_bq2 (23:16), ch4_bq2 (15:8),

ch4_bq2 (7:0)

0x00, 0x80, 0x00, 0x00

6.17 Biquad Filters Register (0x51 – 0x88)

Table 6−18. Biquad Filters Registers Format (0x51 – 0x88)

I2C

SUBADDRESS

TOTAL

BYTES

DESCRIPTION OF CONTENTS

DEFAULT

STATE

0x51–0x57

20/Reg.

Ch1_bq[1] – [7]

Ch 1 Biquads 1 – 7. See Table 6−19 for bit definition.

See Table 6−19

0x58–0x5E

20/Reg.

Ch2_bq[1] – [7]

Ch 2 Biquads 1 – 7. See Table 6−19 for bit definition.

See Table 6−19

0x7B–0x81

20/Reg.

Ch3_bq[1] − [7]

Ch 3 Biquads 1 – 7. See Table 6−19 for bit definition.

See Table 6−19

0x82–0x88

20/Reg.

Ch4_bq[1] − [7]

Ch 4 Biquads 1 – 7. See Table 6−19 for bit definition.

See Table 6−19

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