TAS5504_06 datasheet(59/96 Pages) TI

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Serial Audio Interface Control and Timing

SLES123 − October 2004

TAS5504

3.7.3 Right Justified

Right justified (RJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and

when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock

running at 64 × Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for

24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before

L/RCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5504

masks unused leading data bit positions.

23 22

SCLK

32 Clks

LRCLK

Left Channel

24-Bit Mode

19 18

15 14

19 18

20-Bit Mode

15 14

16-Bit Mode

15 14

MSB

LSB

2-Channel Right-Justified (Sony Format) Stereo Input

23 22

32 Clks

Right Channel

19 18

15 14

19 18

15 14

MSB

LSB

NOTE: All data presented in 2s complement form with MSB first.

Figure 3−11. Right Justified 64 Fs Format

TAS5504 bảng dữ liệu(PDF) 59 Page - Texas Instruments