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ZAMC4100GA2R bảng dữ liệu(PDF) 134 Page - Renesas Technology Corp |
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ZAMC4100GA2R bảng dữ liệu(HTML) 134 Page - Renesas Technology Corp |
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134 / 156 page  ZAMC4100 Datasheet © 2016 Integrated Device Technology, Inc. 134 January 26, 2016 Table 4.27 Register [0x4000_1808] Z1_LINDATA Z1_LINDATA ADD:0x4000_1808 Bit Name Ext. Access Int. Access Reset Value Description 7 : 0 LINDATA R / W R / W 0 When writing a byte to this register, the value is stored in the TX buffer. A WRITE access to this register also clears the TXEMPTY flag in the Z1_LINSTAT register (Table 4.26). When reading this register, the content of the RX buffer is returned. A READ access to this register also clears the RXFULL flag in the Z1_LINSTAT register. Note: When writing to this register if TX buffer is full, the TX buffer keeps its contents and the written byte is rejected. This is signaled by the WRCOLL flag in the Z1_LINSTAT register. 31 : 8 --- R --- 0 Unused; always read as 0. Table 4.28 Register [0x4000_180C] Z1_LINIRQEN Z1_LINIRQEN ADD:0x4000_180C Bit Name Ext. Access Int. Access Reset Value Description 0 SYNCDET R / W R 0 When set to 1, the corresponding status bit is allowed to drive the IRQ output. 1 RXFULL R / W R 0 When set to 1, the corresponding status bit is allowed to drive the IRQ output. 2 TXEMPTY R / W R 0 When set to 1, the corresponding status bit is allowed to drive the IRQ output. 3 CONFLICT R / W R 0 When set to 1, the corresponding status bit is allowed to drive the IRQ output. 4 RXOVERFLOW R / W R 0 When set to 1, the corresponding status bit is allowed to drive the IRQ output. 5 WRCOLL R / W R 0 When set to 1, the corresponding status bit is allowed to drive the IRQ output. 6 TXOFF R / W R 0 When set to 1, the corresponding status bit is allowed to drive the IRQ output. 7 INACTIVE R / W R 0 When set to 1, the corresponding status bit is allowed to drive the IRQ output. 31 : 8 --- R --- 0 Unused; always read as 0. |
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