DSP56600FMSLASHAD datasheet(56/76 Pages) NXP

56 / 76 page

Preliminary

2-14

DSP56652 Technical Data Sheet

MOTOROLA

Specifications

Audio Serial Codec and Baseband Serial Codec Timing

Table 2-13

SAP and BBP Timing

Num

Characteristics

Symbol

Expression

DSP_CLK

@ 58.8

MHz

Case

Unit

Min Max

430

Clock cycle1

tSSICC

´ TDC

i ck

x ck

431

Clock high period

for internal clock

for external clock

´ TDC Ð 12.2

1.5

´ TDC

21.8

25.5

ick

xck

432

Clock low period

for internal clock

for external clock

´ TDC Ð 12.2

1.5

´ TDC

21.8

25.5

ick

xck

433

RXC rising edge to FSR out (bl) high

45.1

26.8

x ck

i ck a

434

RXC rising edge to FSR out (bl) low

45.1

26.8

x ck

i ck a

435

RXC rising edge to FSR out (wr) high2

ÑÑ

47.6

29.3

x ck

i ck a

436

RXC rising edge to FSR out (wr) low2

ÑÑ

47.6

29.3

x ck

i ck a

437

RXC rising edge to FSR out (wl) high

45.9

25.6

x ck

i ck a

438

RXC rising edge to FSR out (wl) low

45.1

26.8

x ck

i ck a

439

Data in setup time before RXC

(SCK in synchronous mode) falling edge

0.0

23.2

x ck

i ck

440

Data in hold time after RXC

falling edge

6.1

3.6

x ck

i ck

441

FSR input (bl, wr) high before RXC

falling edge2

1.2

28.0

x ck

i ck a

442

FSR input (wl) high before RXC

falling edge

1.2

28.0

x ck

i ck a

443

FSR Input hold time after RXC

falling edge

3.6

0.0

x ck

i ck a

444

Flags input setup before RXC

Falling edge

0.0

23.2

x ck

i ck s

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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