DSP56600FMSLASHAD datasheet(19/76 Pages) NXP

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DSP56652

DSP56652 Signal Description

Preliminary

MOTOROLA

DSP56652 Technical Data Sheet

1-13

Ground

Table 1-5

Ground

Ground Names

Description

GNDA

Address bus ground

ÑThese lines connect system ground to the address bus.

GNDB

Smart Card interface ground

ÑThese lines connect system ground to the Smart

Card bus.

GNDC

Bus control ground

ÑThis line connects ground to the bus control logic.

GNDD

Data bus ground

ÑThese lines connect system ground to the data bus.

GNDE

Audio codec port ground

ÑThese lines connect system ground to the audio codec

port.

GNDF

Clock output ground

ÑThis line supplies a quiet ground connection for the clock

output drivers. Ensure that this line connects through an extremely low impedance

path to ground. Use a 0.1

mF bypass capacitor located as close as possible to the chip

package to connect between the VCCF line and the GNDF line.

GNDG

GPIO ground

ÑThese lines connect system ground to GPIO, keypad, data port,

interrupts, STO, and JTAG I/O drivers.

GNDH

Baseband codec and timer ground

ÑThese lines connect system ground to the

baseband codec, timer and QSPI I/O drivers.

GNDK

Emulation port ground

ÑThese lines connect system ground to the emulation port

I/O drivers.

GNDP

Analog PLL circuit ground

ÑThis line supplies a dedicated quiet ground connection

for the analog PLL circuits and must remain relatively noise-free to ensure stable

PLL frequency and performance. Ensure that this line connects through an

extremely low impedance path to ground. Use a 0.1

mF capacitor and a 0.01 mF

capacitor located as close as possible to the chip package to connect between the

VCCP line and the GNDP line.

GNDP1

Analog PLL circuit ground

ÑThis line supplies a dedicated quiet ground connection

for the analog PLL circuits and must remain relatively noise-free to ensure stable

PLL frequency and performance. Ensure that this line connects through an

extremely low impedance path to ground. Use a 0.1

mF capacitor and a 0.01 mF

capacitor located as close as possible to the chip package to connect between the

VCCP line and the GNDP line.

GNDQ

Quiet ground

ÑThese lines supply a quiet ground connection for the internal logic

circuits. Ensure that this line connects through an extremely low impedance path to

ground. Use a 0.1

mF bypass capacitor located as close as possible to the chip

package to connect between the VCCQ line and the GNDQ line.

GND

Substrate ground

ÑThese lines must be tied to ground.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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