DSP56600FMSLASHAD datasheet(23/76 Pages) NXP

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DSP56652

DSP56652 Signal Description

Preliminary

MOTOROLA

DSP56652 Technical Data Sheet

1-17

Reset, Mode, and Multiplexer Control

Table 1-11

Reset, Mode, and Multiplexer Control Signals

Signal Name

Signal

Type

State

during

Reset

Signal Description

RESET_IN

Input

Reset input

ÑThis signal is an active low Schmitt trigger input

that provides a reset signal to the internal circuitry. The input is

valid if it is asserted for at least three CKIL clock cycles.

This pin has a 47k

W pull-up resistor.

Note:

If MUX_CTL is held high, the RTS signal of the serial data

port (UART) becomes the RESET_IN input line.

(See Table 1-15 on page 1-26.)

RESET_OUT

Output

Pulled

low

Reset output

ÑThis signal is asserted low for at least seven CKIL

clock cycles under one of the following conditions:

RESET_IN is pulled low for at least three CKIL clock

cycles

The alternate RESET_IN signal is enabled by MUX_CTL

and is pulled low for at least three CKIL clock cycles

The watchdog count expires

This signal is asserted immediately after the qualifier detects a

valid RESET_IN signal, remains asserted during RESET_IN

assertion, and is stretched for at least seven more CKIL clock

cycles after RESET_IN is deasserted. Three CKIL clock cycles

before RESET_OUT is deasserted, the MCU boot mode is latched

from the MOD signal.

MOD

Input

Mode select

ÑThis signal selects the MCU boot mode during

hardware reset. If MOD is driven low at least four CKIL clock

cycles before RESET_OUT is deasserted, then the internal MCU

ROM ignores the first access and the M¥CORE fetches the first

word from the first location the external Flash memory. If MOD is

driven high four CKIL clock cycles before RESET_OUT

deassertion, then the internal MCU ROM is enabled and the

M¥CORE fetches the first word from the first location in the

internal ROM.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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