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DSP56600FM/AD bảng dữ liệu(PDF) 57 Page - NXP Semiconductors |
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DSP56600FM/AD bảng dữ liệu(HTML) 57 Page - NXP Semiconductors |
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57 / 76 page ![]() Specifications Audio Serial Codec and Baseband Serial Codec Timing Preliminary MOTOROLA DSP56651 Technical Data Sheet 2-15 446 TXC rising edge to FST out (bl) high — — — — 35.4 18.3 x ck i ck ns ns 447 TXC rising edge to FST out (bl) low — — — — 37.8 20.7 x ck i ck ns ns 448 TXC rising edge to FST out (wr) high2 —— — — 37.8 20.7 x ck i ck ns ns 449 TXC rising edge to FST out (wr) low2 —— — — 40.3 23.2 x ck i ck ns ns 450 TXC rising edge to FST out (wl) high — — — — 36.6 19.5 x ck i ck ns ns 451 TXC rising edge to FST out (wl) low — — — — 37.8 20.7 x ck i ck ns ns 452 TXC rising edge to data out enable from high impedance —— — — 37.8 20.7 x ck i ck ns ns 454 TXC rising edge to data out valid — 35 + 0.5 × TDC — — 43.5 25.6 x ck i ck ns ns 455 TXC rising edge to data out high impedance3 —— — — 37.8 19.5 x ck i ck ns ns 457 FST input (bl, wr) setup time before TXC falling edge2 — — 2.0 21.0 — — x ck i ck ns ns 458 FST input (wl) to data out enable from high impedance3 — — — 32.9 — ns 460 FST input (wl) setup time before TXC falling edge — — 2.0 21.0 — — x ck i ck ns ns 461 FST input hold time after TXC falling edge — — 4.0 0.0 — — x ck i ck ns ns 462 Flag output valid after TXC rising edge — — — — 39.0 22.0 x ck i ck ns ns Note: 1. For internal clock, external clock cycle is defined by ICYC and BBP/SAP control register. 2. Word relative frame sync signal wave form, relates to clock, as the bit length frame sync signal wave form, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 3. Periodically sampled and not 100% tested. Table 2-13 SAP and BBP Timing (Continued) Num Characteristics Symbol Expression DSP @ 58.8 MHz Case Unit Min Max Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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