DSP56600FMSLASHAD datasheet(47/76 Pages) NXP

47 / 76 page

Specifications

Internal Clocks

Preliminary

MOTOROLA

DSP56651 Technical Data Sheet

2-5

INTERNAL CLOCKS

For each occurrence of TDH, TDL, TDC, or IDCYC, substitute with the numbers in

Table 2-6

. DF, MF, and PDF are the DSP PLL division, multiplication, and pre-

division factors set in registers.

Table 2-5

DSP Clocks

Characteristics

Symbol

Min

Max

Unit

DSP PLL input frequency

EfD

16.8

MHz

DSP PLL input clock cycle time

• with PLL disabled

• with PLL enabled

ETDC

59.5

∞

273100

Table 2-6

Internal DSP Clocks

Characteristics

Symbol

Expression

Internal DSP operation frequency with PLL enabled

(EfD

× MF) / (PDF × DF)

Internal DSP operation frequency with PLL

disabled

EfD/2

Internal DSP clock high period

• with PLL disabled

• with PLL enabled and MF

≤ 4

• with PLL enabled and MF > 4

TDH

ETDC

(Min) 0.49

× ET

DC × PDF × DF/MF

(Max) 0.51

× ET

DC × PDF × DF/MF

(Min) 0.47

× ET

DC × PDF × DF/MF

(Max) 0.53

× ET

DC × PDF × DF/MF

Internal clock low period

• with PLL disabled

• with PLL enabled and MF

≤ 4

• with PLL enabled and MF > 4

TDL

ETDC

(Min) 0.49

× ET

DC × PDF × DF/MF

(Max) 0.51

× ET

DC × PDF × DF/MF

(Min) 0.47

× ET

DC × PDF × DF/MF

(Max) 0.53

× ET

DC × PDF × DF/MF

Internal clock cycle time with PLL enabled

TDC

ETDC × PDF × DF/MF

Internal clock cycle time with PLL disabled

TDC

× ET

DSP instruction cycle time

IDCYC

TDC

Table 2-7

MCU Clocks

Characteristics

Symbol

Min

Max

Unit

Frequency of the internal MCU-CLK clock

16.8

MHz

Internal MCU-CLK clock cycle time

TMC

59.5

∞

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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