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DSP56600FM/AD bảng dữ liệu(PDF) 22 Page - NXP Semiconductors |
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DSP56600FM/AD bảng dữ liệu(HTML) 22 Page - NXP Semiconductors |
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22 / 76 page ![]() Preliminary 1-16 DSP56651 Technical Data Sheet MOTOROLA Pin and Signal Descriptions DSP56651 Signal Description Chip Selects Table 1-10 Chip Select Signals Signal Name Signal Type State during Reset Signal Description CS0 Output Chip- driven Chip select 0— This signal is asserted low based on the decode of the internal address bus bits A[31:24] and is typically used as the external flash memory chip select. After reset, accesses using this CS have a default of 15 wait states. CS1–CS4 Output Driven high Chip select 1–chip select 4— These signals are asserted low based on the decode of the internal address bus bits A[31:24] of the access address. When not selected as chip select signals, these signals become general purpose outputs (GPOs). After reset, these signals are GPOs that are driven high. CS5 Output Driven low Chip select 5— This signal is asserted high based on the decode of the internal address bus bits A[31:24] of the access address. When not selected as a chip select signal, this signal becomes a GPO. After reset, this signal is a GPO that is driven low. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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