DA16200 datasheet(60/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

60 of 153

THD;STA

SDA

SCL

TSU;DAT

THIGH

TLOW

THD;DAT

TVD;ACK

cont.

...

SDA

SCL

cont.

...

TSU;STA

THD;STA

TBUF

TSU;STO

Figure 34: I2C Slave Timing Diagram

Table 45 lists the I2C slave timing parameters.

Table 45: I2C Slave Timing Parameters

Parameter

Symbol

Fast Mode

High Speed Mode

Unit

Min

Max

Min

Max

SCL clock frequency

FSCLK

100

400

100

3400

(Note 2)

kHz

Clock Duty (Note 1)

Hold time of START

THD;STA

0.6

0.26

μs

Low period of the SCL clock

TLOW

1.3

0.15

μs

High period of the SCL clock

THIGH

1.2

0.14

μs

Setup time for START condition

TSU;STA

0.6

0.26

μs

Data hold time

THD;DAT

μs

Data setup time

TSU;DAT

0.1

0.05

μs

Rise time of both SDA and SCL

0.02

0.3

0.12

μs

Setup time for STOP condition

TSU;STO

0.6

0.26

μs

Data valid acknowledge time

TVD;ACK

μs

Buffer free time between

START and STOP condition

TBUF

1.3

0.5

μs

Note 1

Clock duty ratio = (THIGH/TSCLK) × 100[%], TSCLK = 1/FSCLK.

Note 2

Max. clock = 3.4 MHz (TSCLK = 294 ns) over 40 MHz of the Fop_clk.

Max. clock = 1.0 MHz (TSCLK = 1000 ns) under 40 MHz of the Fop_clk.

9.5.3

Interface Pull-up

The I2C interface requires pull-up resistors to be connected between the signal lines and the supply

to enable communication.

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