DA16200 datasheet(5/154 Pages) RENESAS

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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

5 of 153

7.4.1

Wake-up Controller .............................................................................................. 38

7.4.2

Retention I/O Function......................................................................................... 39

7.5

Pulse Counter ..................................................................................................................... 40

7.5.1

Introduction .......................................................................................................... 40

7.5.2

Functional Description ......................................................................................... 40

7.6

HW Accelerators ................................................................................................................. 41

7.6.1

Zeroing of SRAM ................................................................................................. 41

7.6.2

CRC Calculation .................................................................................................. 41

7.6.3

Pseudo Random Number Generator (PRNG) ..................................................... 41

7.7

DMA Operation ................................................................................................................... 42

7.7.1

DMA1 ................................................................................................................... 42

7.7.2

DMA2 (Fast DMA) ............................................................................................... 44

7.8

Simple Memory Protection .................................................................................................. 45

7.9

Bus Protection of Serial Slave Interfaces............................................................................ 46

7.10 Watchdog Timer.................................................................................................................. 46

7.11 Clock Generator .................................................................................................................. 48

Crypto Engine .............................................................................................................................. 49

Peripherals ................................................................................................................................... 50

9.1

QSPI Master with XIP Feature ............................................................................................ 50

9.2

SPI Master .......................................................................................................................... 52

9.3

SPI Slave ............................................................................................................................ 53

9.4

SDIO.................................................................................................................................... 56

9.5

I2C Interface........................................................................................................................ 58

9.5.1

I2C Master ........................................................................................................... 58

9.5.2

I2C Slave ............................................................................................................. 59

9.5.3

Interface Pull-up................................................................................................... 60

9.6

SD/eMMC............................................................................................................................ 61

9.6.1

Block Diagram ..................................................................................................... 61

9.7

I2S ....................................................................................................................................... 62

9.7.1

Block Diagram ..................................................................................................... 63

9.7.2

I2S Clock Scheme ............................................................................................... 64

9.7.3

I2S Transmit and Receive Timing Diagram......................................................... 65

9.8

ADC (Aux 12-bit) ................................................................................................................. 67

9.8.1

Overview .............................................................................................................. 67

9.8.2

Timing Diagram ................................................................................................... 67

9.8.3

DMA Transfer ...................................................................................................... 68

9.8.4

Sensor Wake-up .................................................................................................. 68

9.8.5

ADC Ports ............................................................................................................ 68

9.9

GPIO ................................................................................................................................... 69

9.9.1

Antenna Switching Diversity ................................................................................ 69

9.10 UART

9.10.1

RS-232................................................................................................................. 72

9.10.2

RS-485................................................................................................................. 72

9.10.3

Baud Rate ............................................................................................................ 73

9.10.4

Hardware Flow Control ........................................................................................ 73

9.10.5

Interrupts.............................................................................................................. 74

9.10.6

DMA Interface ...................................................................................................... 74

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