DA16200 datasheet(56/154 Pages) RENESAS

56 / 154 page

DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

56 of 153

9.4

SDIO

SDIO is a full/high speed card suitable for memory card and I/O card applications with low power

consumption. The full/high speed card supports SPI, 1-bit SD, and 4-bit SD transfer modes at the full

clock range of 0 to 50 MHz. To be compatible with the serviceable SDIO clock, the internal BUS

clock needs to be set to minimum 50 MHz. The CIS and CSA areas are located inside the internal

memory and the SDIO registers (CCCR and FBR) are programmed by the SD host.

Command

Decoder

APB bus

Interface

REG.

Control

Fn0 / Fn1

Decoder

DAT

Decoder

Response

Generator

CRC

Generator

2 port

Memory

DMA

Controller

Figure 30: SDIO Slave Block Diagram

Table 40 shows the pin definition of the SDIO interface.

The GPIOA4 and GPIOA5 pins are set to SDIO CMD and CLK by default. If SDIO initialization is

done and SDIO communication is enabled, then the SDIO data pin setting is done automatically. In

other words, when the SDIO communication is detected, the pin used as the SDIO data among the

GPIO pins is automatically activated in the SDIO use mode. However, the auto setting function is not

supported for the F_xxx pin used as the flash function.

Table 40: SDIO Slave Pin Configuration

Pin Name

Pin Number

I/O

Function Name

QFN

fcCSP

GPIOA4

I/O

SDIO_CMD

GPIOA5

SDIO_CLK

GPIOA9

I/O

SDIO_D0

GPIOA8

I/O

SDIO_D1

GPIOA7

I/O

SDIO_D2

GPIOA6

I/O

SDIO_D3

DA16200 bảng dữ liệu(PDF) 56 Page - Renesas Technology Corp

DA16200 bảng dữ liệu(HTML) 56 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL