UPSD3422EB40U6 datasheet(246/300 Pages) STMICROELECTRONICS

246 / 300 page

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PSD module

UPSD3422, UPSD3433, UPSD3434, UPSD3454

246/300

Figure 86.

Port C structure

Note:

Optional function on a specific Port C pin.

28.5.51

Port D structure

Port D has two I/O pins (PD1, PD2) on 80-pin UPSD34xx devices, and just one pin (PD1) on

52-pin devices, supporting the following operating modes:

●

MCU I/O Mode

●

DPLD Output Mode for External Chip Selects, ECS1, ECS2. This does not consume

OMCs in the GPLD.

●

PLD Input Mode – direct input to the PLD Input Bus available to DPLD and GPLD. Does

not use IMCs

See Figure 87 on page 247 for detail.

I/O port C

logic

Direction

Drive Select

Data out

(MCUI/O)

Enable Out

Data in (MCUI/O)

PT Output Enable, .OE (JTAG state machine

automatically controls OE for JTAG signals)

Output

Enable

Typical

pin,

port C

PSD module reset

One of 6

CSIOP

registers

From OMC output (MCELLBCx)

From Flash memories

TO/From JTAG

state machine

From PLD

input bus

From AND-

OR array

From OMC

allocator

CLR

Direction

Drive

(MCUI/O)

data out

8032

Reset

PSDsoft

8032 RD

To IMCs

CSIOP

registers

Drive type select

(2)

8032

data

bits

8032

DATA

BIT

INPUT

CMOS

buffer

hysteresis

VDD

output

50k

Pull-up

only on

JTAG TDI,

TMS, TCK

signals

IMCC2, IMCC3,

IMCC4, IMCC7

RDY/BSY

(1)

TDO, TSTAT

(1), TERR(1)

TDI, TMS, TCK

AI09181c

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Product(s)

- Obsolete

Product(s)

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