UPSD3422EB40U6 datasheet(245/300 Pages) STMICROELECTRONICS

245 / 300 page

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Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

PSD module

245/300

28.5.50

Port C structure

Port C supports the following operating modes on pins PC2, PC3, PC4, PC7:

●

MCU I/O Mode

●

GPLD Output Mode from Output Macrocells MCELLBC2, MCELLBC3, MCELLBC4,

MCELLBC7

●

GPLD Input Mode to Input Macrocells IMCC2, IMCC3, IMCC4, IMCC7

See Figure 86 on page 246 for detail.

Port C pins can also be configured in PSDsoft for other dedicated functions:

●

Pins PC3 and PC4 support TSTAT and TERR status indicators, to reduce the amount

of time required for JTAG ISP programming. These two pins must be used together for

this function, adding to the four standard JTAG signals. When TSTAT and TERR are

used, it is referred to as “6-pin JTAG”. PC3 and PC4 cannot be used for other functions

if they are used for 6-pin JTAG. See Section 28.6.1: JTAG ISP and JTAG debug on

page 257 for details.

●

PC3 can be used as an output to indicate when a Flash memory program or erase

operation has completed. This is specified in PSDsoft Express as Section 28.5.13:

Ready/Busy (PC3) on page 215.

The remaining four pins (TDI, TDO, TCK, TMS) on Port C are dedicated to the JTAG

function and cannot be used for any other function. See Section 28.6.1: JTAG ISP and JTAG

debug on page 257.

Port C also supports the Open Drain output drive type options on pins PC2, PC3, PC4, and

PC7 using the csiop Drive Select registers.

Obsolete

Product(s)

- Obsolete

Product(s)

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