UPSD3422EB40U6 datasheet(243/300 Pages) STMICROELECTRONICS

243 / 300 page

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28.5.47

Individual port structures

Ports A, B, C, and D have some differences. The structure of each individual port is

described in the next sections.

28.5.48

Port A structure

Port A supports the following operating modes:

●

MCU I/O Mode

●

GPLD Output Mode from Output Macrocells MCELLABx

●

GPLD Input Mode to Input Macrocells IMCAx

●

Latched Address Output Mode

●

Peripheral I/O Mode

Port A also supports Open Drain/Slew Rate output drive type options using csiop Drive

Select registers. Pins PA0-PA3 can be configured to fast slew rate, pins PA4-PA7 can be

configured to Open Drain Mode.

See Figure 84 for details.

Figure 84.

Port A structure

Note:

Port pins PA0-PA3 are capable of Fast Slew Rate output drive option. Port pins PA4-PA7 are

capable of Open Drain output option.

I/O port A

logic

Direction

Drive Select

Control

Data out

(MCUI/O)

Enable Out

Data in (MCUI/O)

D bit, periph I/O mode

PT Output Enable (.OE)

Latched addr bit

MUX

Output

Enable

Typical

pin, port A

PSD module reset

One of 6

CSIOP

registers

Output

select

Peripheral I/O

mode sets

direction

From OMC output (MCELLABx)

From PLD

input bus

From AND-

OR array

From OMC

allocator

CLR

Direction

Drive

Control

(MCUI/O)

Data out

8032

Reset

PSDsoft

8032 RD

PSELx

PERIPH I/O

DATA BIT

TO IMCs

PIO EN

CSIOP

registers

Drive type select

(1)

8032

Data

bits

8032

Data

bit

Pin input

CMOS

buffer

hysteresis

VDD

output

1 = open

drain,

PA4 - PA7

1 = Fast

Slew rate,

PA0 - PA3

IMCA0 - IMCA7

AI09179b

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