UPSD3422EB40U6 datasheet(239/300 Pages) STMICROELECTRONICS

239 / 300 page

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UPSD3422, UPSD3433, UPSD3434, UPSD3454

PSD module

239/300

28.5.41

Peripheral I/O mode

This mode will provide a data bus repeater function for the 8032 to interface with external

parallel peripherals. The mode is only available on Port A (80-pin devices only) and the data

bus signals, D0 - D7, are de-multiplexed (no address A0-A7). When active, this mode

behaves like a bidirectional buffer, with the direction automatically controlled by the 8032 RD

and WR signals for a specified address range. The DPLD signals PSEL0 and PSEL1

determine this address range. Figure 79 on page 232 shows the action of Peripheral I/O

mode on the Output Enable logic of the tri-state output driver for a single port pin. Figure 83

on page 239 illustrates data repeater the operation. To activate this mode, choose the pin

function “Peripheral I/O Mode” in PSDsoft Express on any Port A pin (all eight pins of Port A

will automatically change to this mode). Next in PSDsoft, specify an address range for the

PSELx signals in the “Chip-Select” section of the “Design Assistant”. The user can specify

an address range for either PSEL0 or PSEL1. Always qualify the PSELx equation with

“PSEN is logic '1'” to ensure Peripheral I/O mode is only active during 8032 data cycles, not

code cycles. Only one equation is needed since PSELx signals are OR’ed together

(Figure 83). Then in the 8032 initialization firmware, a logic ’1’ is written to the csiop VM

automatically perform this repeater function whenever the 8032 presents an address (and

memory page number, if paging is used) that is within the range specified by PSELx. Once

Port A is designated as Peripheral I/O mode in PSDsoft Express, it cannot be used for other

functions.

Note:

The user can alternatively connect an external parallel peripheral to the standard 8032 AD0-

AD7 pins on an 80-pin uPSD device (not Port A), but these pins have multiplexed address

and data signals, with a weaker fanout drive capability.

Figure 83.

Peripheral I/O mode

Table 191.

Latched address output, port B contro register(1) (2)(address = csiop +

offset 03h)l

Default state for register is 00h after reset or power-up.

For each bit, 1 = drive demuxed 8032 address signal on pin, 0 = pin is default mode, MCU I/O.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PB7

(addr A7 or

A15)

PB6

(addr A6 or

A14)

PB5

(addr A5 or

A13)

PB4

(addr A4 or

A12)

PB3

(addr A3 or

A11)

PB2

(Addr A2

or A10)

PB1

(addr A1 or

A9)

PB0

(addr A0 or

A8)

PSEL1

Port

A pins

PA0 - PA7

PSEL0

VM register bit 7 (PIO EN)

8032 RD

8032 WR

8032 data

bus D0-D7

(DE-MUXED)

AI02886A

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