UPSD3422EB40U6 datasheet(242/300 Pages) STMICROELECTRONICS

242 / 300 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

Product(s)

- Obsolete

Product(s)

PSD module

UPSD3422, UPSD3433, UPSD3434, UPSD3454

242/300

Table 193.

Port B pin drive select register (address = csiop + offset 09h)(1) (2)

For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull.

Default state for register is 00h after reset or power-up.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PB7

open drain

PB6

open drain

PB5

open drain

PB4

open drain

PB3

slew rate

PB2

slew rate

PB1

slew rate

PB0

slew rate

Table 194.

Port C pin drive select register (address = csiop + offset 16h)(1) (2)

For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull

Default state for register is 00h after reset or power-up

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PC7

open drain

N/A

(JTAG)

N/A

(JTAG)

PC4

open drain

PC3

open drain

PC2

open drain

N/A

(JTAG)

N/A

(JTAG)

Table 195.

Port D pin drive select register (address = csiop + offset 17h)(1) (2)

For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull

Default state for register is 00h after reset or power-up

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

N/A

PD2(3)

slew rate

Pin is not available on 52-pin UPSD34xx devices

PD1

slew rate

N/A

Table 196.

Port A enable out register(1) (2)(address = csiop + offset 0Ch)

Port A not available on 52-pin UPSD34xx devices

For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PA7 OE

PA6 OE

PA5 OE

PA4 OE

PA3 OE

PA2 OE

PA1 OE

PA0 OE

Table 197.

Port B enable out register (address = csiop + offset 0Dh)(1)

For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PB7 OE

PB6 OE

PB5 OE

PB4 OE

PB3 OE

PB2 OE

PB1 OE

PB0 OE

Table 198.

Port C enable out register (address = csiop + offset 1Ah)(1)

For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PC7 OE

N/A

(JTAG)

N/A

(JTAG)

PC4 OE

PC3 OE

PC2 OE

N/A

(JTAG)

N/A

(JTAG)

Table 199.

Port D enable out register (address = csiop + offset 1Bh)(1)

For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

N/A

PD2 OE(2)

Pin is not available on 52-pin UPSD34xx devices

PD1 OE

N/A

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD3422EB40U6 bảng dữ liệu(PDF) 242 Page - STMicroelectronics

UPSD3422EB40U6 bảng dữ liệu(HTML) 242 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL