UPSD3422EB40U6 datasheet(54/300 Pages) STMICROELECTRONICS

54 / 300 page

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UPSD34xx instruction set summary

UPSD3422, UPSD3433, UPSD3434, UPSD3454

54/300

Table 8.

Data transfer instruction set

Mnemonic(1) and use

All mnemonics copyrighted ©Intel Corporation 1980.

Description

Length/cycles

MOV

A, Rn

Move register to ACC

1 byte/1 cycle

MOV

A, direct

Move direct byte to ACC

2 byte/1 cycle

MOV

A, @Ri

Move indirect SRAM to ACC

1 byte/1 cycle

MOV

A, #data

Move immediate data to ACC

2 byte/1 cycle

MOV

Rn, A

Move ACC to register

1 byte/1 cycle

MOV

Rn, direct

Move direct byte to register

2 byte/2 cycle

MOV

Rn, #data

Move immediate data to register

2 byte/1 cycle

MOV

direct, A

Move ACC to direct byte

2 byte/1 cycle

MOV

direct, Rn

Move register to direct byte

2 byte/2 cycle

MOV

direct, direct

Move direct byte to direct

3 byte/2 cycle

MOV

direct, @Ri

Move indirect SRAM to direct byte

2 byte/2 cycle

MOV

direct, #data

Move immediate data to direct byte

3 byte/2 cycle

MOV

@Ri, A

Move ACC to indirect SRAM

1 byte/1 cycle

MOV

@Ri, direct

Move direct byte to indirect SRAM

2 byte/2 cycle

MOV

@Ri, #data

Move immediate data to indirect SRAM

2 byte/1 cycle

MOV

DPTR,

#data16

Load Data Pointer with 16-bit constant

3 byte/2 cycle

MOVC

A, @A+DPTR Move code byte relative to DPTR to ACC

1 byte/2 cycle

MOVC

A, @A+PC

Move code byte relative to PC to ACC

1 byte/2 cycle

MOVX

A, @Ri (2)

This instruction is not supported by UPSD34xx. See Section 9.6: External indirect addressing on page 49

Move XDATA (8-bit addr) to ACC

1 byte/2 cycle

MOVX

A, @DPTR

Move XDATA (16-bit addr) to ACC

1 byte/2 cycle

MOVX

@Ri, A (2)

Move ACC to XDATA (8-bit addr)

1 byte/2 cycle

MOVX

@DPTR, A

Move ACC to XDATA (16-bit addr)

1 byte/2 cycle

XCH

A, Rn

Exchange register with ACC

1 byte/1 cycle

PUSH

direct

Push direct byte onto stack

2 byte/2 cycle

POP

direct

Pop direct byte from stack

2 byte/2 cycle

XCH

A, direct

Exchange direct byte with ACC

2 byte/1 cycle

XCH

A, @Ri

Exchange indirect SRAM with ACC

1 byte/1 cycle

XCHD

A, @Ri

Exchange low-order digit indirect SRAM with

ACC

1 byte/1 cycle

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