SM8521 datasheet(49/56 Pages) SHARP

49 / 56 page

SM8521

- 49 -

UART Control Register (URTC)

Control register URTC is an 8-bit readable/writable

transmit/receive operation controlling.

Bit 7

Bits 7 to 5 : Set ‘0’.

Bit 4 : Transmit enable bit (TE)

Setting the bit TE to ‘1’, starts the built-in baud

rate

generator

and

the

interface

enters

transmissible status. In such status, if a transmit

data is written to the transmit data register

URTT, then will start the transmission operation.

If the bit TE clears to ‘0’, the transmitter will be

initializated.

Bit 3 : Receive enable bit (RE)

Setting the bit RE to ‘1’, starts the built-in baud

rate

generator

and

the

interface

enters

receivable status. In such status, if the start bit

(= ‘0’) is detected, then will start the receive

operation.

If the bit RE clears to ‘0’, the receiver will be

initializated.

Bit 2 : Parity enable bit (PEN)

Bit 1 : Even/odd parity bit (EOP)

Bit 0 : Stop bit length bit (SBL)

PEN EOP SBL

BIT

CONTENT

Transmitter disable

Transmitter enable

(built-in baud rate generator operates)

BIT

CONTENT

Receiver disable

Receiver enbable

(built-in baud rate generator operates)

BIT

CONTENT

Transmit : the data with parity bit

Receive : parity enable

Transmit : the data without parity bit

Receive : parity disable

BIT

CONTENT

Even parity

Odd parity

BIT

CONTENT

Stop bit : 1 bit

Stop bit : 2 bits

SM8521 bảng dữ liệu(PDF) 49 Page - Sharp Corporation

SM8521 bảng dữ liệu(HTML) 49 Page - Sharp Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

bảng dữ liệu tải về

Link URL