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SM8521 bảng dữ liệu(PDF) 29 Page - Sharp Corporation |
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SM8521 bảng dữ liệu(HTML) 29 Page - Sharp Corporation |
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29 / 56 page ![]() SM8521 - 29 - P0 to P3 (PIO data register) Bit 7 0 (x = 0, 1, 2, 3) NOTE : In case of reading P0-P3 register on condition that control register is input state, data of those pins is read. In case of on condition that control register is output state, data of register is read. P0C to P2C (PIO control register) Bit 7 0 (x = 0, 1, 2) Bits 7 to 6 : Bits 5 to 4 : Bits 3 to 2 : Bits 1 to 0 : I/O PORTS The SM8521 supports four 8-bit I/O ports. Each port can be selected one out of input, outpit, input with built-in pull-up resistor and open-drain in each 2-bit. Internal Bus Input/output pins Data register I/O control circuit Control register Fig. 12 PIO Block Diagram PX7PX6PX5PX4PX3PX2PX1PX0 PXC7 PXC6 PXC5 PXC4 PXC3 PXC2 PXC1 PXC0 BIT CONTENT 00 Input 01 10 11 Input (with pull-up resistor) Output Output (open-drain) BIT CONTENT 00 Input 01 10 11 Input (with pull-up resistor) Output Output (open-drain) BIT CONTENT 00 Input 01 10 11 Input (with pull-up resistor) Output Output (open-drain) BIT CONTENT 00 Input 01 10 11 Input (with pull-up resistor) Output Output (open-drain) |
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