SM8521 datasheet(23/56 Pages) SHARP

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SM8521

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Hardware Reset

The hardware reset is an initial function for SM8521

system and comes from the following sources.

• External reset

If the RESETB pin is applied to Low level in

SM8521 operating, the hardware resets.

• Watchdog timer overflow

While watchdog timer overflows, the hardware

resets.

The above 2 hardware reset sources initializate the

system.

OPERATING EXPLANATIONS

• Hardware reset operation

When the SM8521 is operating, a built-in pull-up

resistor keeps the RESETB pin at High level. If

external circuit (like as reset IC etc.) applies Low

level voltage to RESETB pin, the SM8521 is reset

by hardware after approximately two instruction

cycles. To ensure hardware reset execution keeps

the RESETB pin at Low level over two instruction

cycles of system clock.

The pin back to High level from Low level starts the

warming up counter built-in SM8521. When the

counter overflows, about 218 x main-clock leaves its

hardware reset state and begins the program

execution from the instruction at address 1020H. In

the warming up interval, SM8521 is in HALT mode

state.

Same as watchdog timer overflow case, the CPU

leaves the hardware reset behind warming up period.

Interrupt Function

The SM8521 supports 10 interrupt sources.

In these interrupts, watchdog timer and illegal

instruction trap interrupts belong to non-maskable

interrupts, the others, however, are maskable

interrupts. 10 interrupt sources are shared to

independent interrupt vector respectively, in the

ROM address area between 1000H-101FH. And, the

maskable interrupts are set 8 steps with priority

level.

With priority 8 levels

With priority 1 level

WDT (NMI)

PS0

PS1

Illegal instruction trap

Interrupt signal

Interrupt process

IE0

IE1

IR0

IR1

Interrupt request register

Interrupt enable register

Fig. 10

Interrupt Block Diagram

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