SM8521 datasheet(37/56 Pages) SHARP

37 / 56 page

SM8521

- 37 -

Registers

LCDC/DMA registers are shown below. LCDC

setting each parameter, set the DMA start bit to ‘1’

and execute HALT instruction, then DMA transfer

starts.

LCC (LCD control/status register)

Bit 7

Bit 7 : Display ON/OFF

Bit 6 : Display page A/B bit

Bits 5 to 4 : Gradation control bits

(Depth of black and white on real LCD)

NOTE : Gray scale

White

Gray3

Gray2

Gray1

Black

Bits 3 to 1 : LCDC/DMA clock bits

Bit 0 : Normal white bar bit

LCH (Display horizontal timing register)

Bit 7

Bits 7 to 6 : Set ‘0’.

Bit 5 : H-dot size bit

Bits 4 to 0 : H-timing bits

NOTE :

V-blank width bit must not be filled with 0000B. Otherwise,

LCDC interrupt can not be effective.

Horizontal display cycle = (shift clock x LCDC/DMA

clock ) x (H-timing + 1)

Shift clock = 40 (at H-dot size = 160),

50 (at H-dot size = 200)

Frame cycle = Horizontal display cycle x (V-line

size + V-blank width)

Gray 3

Gray 2

White

Black

Gray 1

Gray 2

Gray 1

DISON DISPG GRAD1 GRAD0 LCCL2 LCCL1 LCCL0 NORWH

HD0T HTIM4 HTIM3 HTIM2 HTIM1 HTIM0

BIT

HORIZONTAL DOT SIZE

160

200

BIT

STATUS

Normal white

Normal black

BIT

LCDC/DMA CLOCK

000

fCK/2

001

010

011

100

101

110

111

fCK/4

fCK/6

fCK/8

fCK/10

fCK/12

fCK/14

fCK/16

BIT

DISPLAY PAGE

Page A

Page B

BIT

DISPLAY ON/OFF

Display OFF

Display ON

BIT

Gray 3

White

GRADATION CHOOSEN

Reserved

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