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NRF9160-SICA-R7 bảng dữ liệu(PDF) 104 Page - Nordic Semiconductor |
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NRF9160-SICA-R7 bảng dữ liệu(HTML) 104 Page - Nordic Semiconductor |
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104 / 400 page ![]() Peripherals 6.4.4.7 DIRCLR Address offset: 0x01C DIR clear register Note: Read: reads value of DIR register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A-f RW PIN[i] (i=0..31) Set as input pin i Input 0 Read: pin set as input Output 1 Read: pin set as output Clear 1 Write: writing a '1' sets pin to input; writing a '0' has no effect 6.4.4.8 LATCH (Retained) Address offset: 0x020 Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers This register is retained. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID f e d c b a Z Y X W V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A-f RW PIN[i] (i=0..31) Status on whether PINi has met criteria set in PIN_CNFi.SENSE register. Write '1' to clear. NotLatched 0 Criteria has not been met Latched 1 Criteria has been met 6.4.4.9 DETECTMODE (Retained) Address offset: 0x024 Select between default DETECT signal behavior and LDETECT mode (For non-secure pin only) This register is retained. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A RW DETECTMODE Select between default DETECT signal behavior and LDETECT mode Default 0 DETECT directly connected to PIN DETECT signals LDETECT 1 Use the latched LDETECT behavior 6.4.4.10 DETECTMODE_SEC (Retained) Address offset: 0x028 Select between default DETECT signal behavior and LDETECT mode (For secure pin only) This register is retained. 4418_1315 v2.0 104 |
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