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NRF9160-SICA-R7 bảng dữ liệu(PDF) 379 Page - Nordic Semiconductor |
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NRF9160-SICA-R7 bảng dữ liệu(HTML) 379 Page - Nordic Semiconductor |
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379 / 400 page ![]() Debug and trace Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A R RXDATA Data received from debugger 9.2.6.2 MAILBOX.RXSTATUS Address offset: 0x404 This register shows a status that indicates if data sent from the debugger to the CPU has been read. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A R RXSTATUS Status of data in register RXDATA NoDataPending 0 No data pending in register RXDATA DataPending 1 Data pending in register RXDATA 9.2.6.3 MAILBOX.TXDATA Address offset: 0x480 Data sent from the CPU to the debugger. Writing to this register will automatically set a DataPending value in the TXSTATUS register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A RW TXDATA Data sent to debugger 9.2.6.4 MAILBOX.TXSTATUS Address offset: 0x484 This register shows a status that indicates if the data sent from the CPU to the debugger has been read. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID Value Description A R TXSTATUS Status of data in register TXDATA NoDataPending 0 No data pending in register TXDATA DataPending 1 Data pending in register TXDATA 9.2.6.5 ERASEPROTECT.LOCK Address offset: 0x500 This register locks the ERASEPROTECT.DISABLE register from being written until next reset. 4418_1315 v2.0 379 |
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