CS47L85 datasheet(117/370 Pages) CIRRUS

117 / 370 page

CS47L85

Rev 4.3

117

ASRCn_IN1R_ENA

ASRCn_IN1L_ENA

ASRCn_IN1L_SRC

ASRCn_IN1R_SRC

ASRC1 IN1L (90h)

ASRC2 IN1L (94h)

ASRC1 IN1R (91h)

ASRC2 IN1R (95h)

ASRCn_IN2R_ENA

ASRCn_IN2L_ENA

ASRCn_IN2L_SRC

ASRCn_IN2R_SRC

ASRC1 IN2L (92h)

ASRC2 IN2L (96h)

ASRC1 IN2R (93h)

ASRC2 IN2R (97h)

ASRCn_RATE1

(= SAMPLE_RATE_n)

ASRCn_RATE2

(= ASYNC_SAMPLE_RATE_n)

The ASRC provides asynchronous conversion between the SYSCLK and ASYNCCLK CLOCK domains.

ASRCn_RATE1 identifies the SYSCLK-related sample rate (SAMPLE_RATE_n).

ASRCn_RATE2 identifies the ASYNCCLK-related sample rate (ASYNC_SAMPLE_RATE_n).

CS47L85 supports 2 ASRC blocks, ie. n = 1 or 2

Figure 38 Asynchronous Sample Rate Converters (ASRCs)

The ASRC1 and ASRC2 input control registers (see Figure 38) are located at register addresses R2688 (A80h) through to

R2744 (AB8h).

The full list of digital mixer control registers (Register R1600 through to R3192) is provided in a separate document - see

“Register Map” for further information. Generic register definitions are provided in Table 8.

The *_SRCn registers select the input source(s) for the respective ASRC processing blocks. Note that the selected input

source(s) must be configured for the same sample rate as the ASRC to which they are connected.

The bracketed numbers in Figure 38,

e.g.,”(90h)” indicate the corresponding *_SRCn register setting for selection of that

signal as an input to another digital core function.

The ASRC paths should be kept disabled (ASRCn_INmx_ENA=0) if SYSCLK is not enabled. The *_SRCn registers for all

digital core functions should be held at 00h if SYSCLK is not enabled

– SYSCLK must be present and enabled before

selecting other values for these registers. See “Clocking and Sample Rates” for further details (including requirements for

reconfiguring SYSCLK while digital core functions are enabled).

The register bits associated with the ASRCs are described in Table 23.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3792

(0ED0h)

ASRC2_E

NABLE

ASRC2_IN2L_EN

ASRC2 IN2 (Left) Enable

(Left ASRC2 channel from ASYNCCLK

domain to SYSCLK domain)

0 = Disabled

1 = Enabled

ASRC2_IN2R_EN

ASRC2 IN2 (Right) Enable

(Right ASRC2 channel from ASYNCCLK

domain to SYSCLK domain)

0 = Disabled

1 = Enabled

ASRC2_IN1L_EN

ASRC2 IN1 (Left) Enable

(Left ASRC2 channel from SYSCLK

domain to ASYNCCLK domain)

0 = Disabled

1 = Enabled

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