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CS47L85 bảng dữ liệu(PDF) 9 Page - Cirrus Logic

tên linh kiện CS47L85
Giải thích chi tiết về linh kiện  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 bảng dữ liệu(HTML) 9 Page - Cirrus Logic

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CS47L85
Rev 4.3
9
PIN NO
NAME
TYPE
DESCRIPTION
P8
AIF4RXDAT/
GPIO29
Digital Input / Output
Audio interface 4 RX digital audio data / GPIO29.
GPIO output is selectable CMOS or Open Drain.
L7
AIF4TXDAT/
GPIO27
Digital Input / Output
Audio interface 4 TX digital audio data / GPIO27.
GPIO output is selectable CMOS or Open Drain;
TXDAT output is CMOS.
H3
AVDD1
Supply
Analogue supply
C14
AVDD2
Supply
Analogue supply
J12
CIF1MISO
Digital Output
Control interface 1 (SPI) Master In Slave Out data.
The CIFMISO is high impedance when CIF1SS
¯¯¯¯¯¯ is not asserted.
J11
CIF1MOSI
Digital Input
Control interface 1 (SPI) Master Out Slave In data
J13
CIF1SCLK
Digital Input
Control interface 1 (SPI) clock input
H11
CIF1SS
¯¯¯¯¯¯
Digital Input
Control interface 1 (SPI) Slave Select (SS)
K11
CIF2SCLK
Digital Input
Control interface 2 (I2C) clock input
K13
CIF2SDA
Digital Input / Output
Control interface 2 (I2C) data input and output.
The SDA output is Open Drain.
L6
CIF3MISO
Digital Output
Control interface 3 (SPI) Master In Slave Out data.
The CIFMISO is high impedance when CIF3SS
¯¯¯¯¯¯ is not asserted.
N6
CIF3MOSI
Digital Input
Control interface 3 (SPI) Master Out Slave In data
N7
CIF3SCLK
Digital Input
Control interface 3 (SPI) clock input
M6
CIF3SS
¯¯¯¯¯¯
Digital Input
Control interface 3 (SPI) Slave Select (SS)
C5
CP1C1A
Analogue Output
Charge pump 1 fly-back capacitor 1 pin
C6
CP1C1B
Analogue Output
Charge pump 1 fly-back capacitor 1 pin
B6
CP1C2A
Analogue Output
Charge pump 1 fly-back capacitor 2 pin
A6
CP1C2B
Analogue Output
Charge pump 1 fly-back capacitor 2 pin
C7
CP1VOUT1N
Analogue Output
Charge pump 1 negative output 1 decoupling pin
C8
CP1VOUT1P
Analogue Output
Charge pump 1 positive output 1 decoupling pin
A7
CP1VOUT2N
Analogue Output
Charge pump 1 negative output 2 decoupling pin
B7
CP1VOUT2P
Analogue Output
Charge pump 1 positive output 2 decoupling pin
D7
CP2CA
Analogue Output
Charge pump 2 fly-back capacitor pin
D6
CP2CB
Analogue Output
Charge pump 2 fly-back capacitor pin
D5
CP2VOUT
Analogue Output
Charge pump 2 output decoupling pin / Supply for LDO2
B5
CPGND
Supply
Charge pump ground (Return path for CPVDD1, CPVDD2)
A5
CPVDD1
Supply
Supply for Charge Pumps 1 & 2
B8
CPVDD2
Supply
Secondary supply for Charge Pump 1
L14
DBVDD1
Supply
Digital buffer (I/O) supply
(core functions, AIF1, CIF1, CIF2, SLIMbus, MIF1, GPIO1)
P13
DBVDD2
Supply
Digital buffer (I/O) supply
(AIF2, PDM, MIF2, MCLK2, GPIO2, JTAG)
P4
DBVDD3
Supply
Digital buffer (I/O) supply (AIF3, AIF4, CIF3, MIF3, GPIO3-8)
P10
DBVDD4
Supply
Digital buffer (I/O) supply (DMIC4, DMIC5, DMIC6)
J14, N14, P5
DCVDD
Supply
Digital core supply
G14, H14,
K14, P6, P7,
P12, P14
DGND
Supply
Digital ground
(Return path for DCVDDn and DBVDDn)
N10
DMICCLK4/
GPIO31
Digital Input / Output
Digital MIC clock output 4 / GPIO31.
GPIO output is selectable CMOS or Open Drain;
DMICCLK output is CMOS.
M9
DMICDAT4/
GPIO32
Digital Input / Output
Digital MIC data input 4 / GPIO32.
GPIO output is selectable CMOS or Open Drain.
N9
DMICCLK5/
GPIO33
Digital Input / Output
Digital MIC clock output 5 / GPIO33.
GPIO output is selectable CMOS or Open Drain;
DMICCLK output is CMOS.
P9
DMICDAT5/
GPIO34
Digital Input / Output
Digital MIC data input 5 / GPIO34.
GPIO output is selectable CMOS or Open Drain.



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