CS47L85 datasheet(33/370 Pages) CIRRUS

tên linh kiện	CS47L85

Giải thích chi tiết về linh kiện	Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub

PDF	370 Pages

Scroll/Zoom	100%

nhà sản xuất	CIRRUS [Cirrus Logic]

Trang chủ	http://www.cirrus.com

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CS47L85

Rev 4.3

Test Conditions

The following timing information is valid across the full range of recommended operating conditions.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Internal Clocking

SYSCLK frequency

SYSCLK_FREQ=000, SYSCLK_FRAC=0

-1%

6.144

+1%

MHz

SYSCLK_FREQ=000, SYSCLK_FRAC=1

-1%

5.6448

+1%

SYSCLK_FREQ=001, SYSCLK_FRAC=0

-1%

12.288

+1%

SYSCLK_FREQ=001, SYSCLK_FRAC=1

-1%

11.2896

+1%

SYSCLK_FREQ=010, SYSCLK_FRAC=0

-1%

24.576

+1%

SYSCLK_FREQ=010, SYSCLK_FRAC=1

-1%

22.5792

+1%

SYSCLK_FREQ=011, SYSCLK_FRAC=0

-1%

49.152

+1%

SYSCLK_FREQ=011, SYSCLK_FRAC=1

-1%

45.1584

+1%

SYSCLK_FREQ=100, SYSCLK_FRAC=0

-1%

98.304

+1%

SYSCLK_FREQ=100, SYSCLK_FRAC=1

-1%

90.3168

+1%

ASYNCCLK frequency

ASYNC_CLK_FREQ=000

-1%

6.144

+1%

MHz

-1%

5.6448

+1%

ASYNC_CLK_FREQ=001

-1%

12.288

+1%

-1%

11.2896

+1%

ASYNC_CLK_FREQ=010

-1%

24.576

+1%

-1%

22.5792

+1%

ASYNC_CLK_FREQ=011

-1%

49.152

+1%

-1%

45.1584

+1%

ASYNC_CLK_FREQ=100

-1%

98.304

+1%

-1%

90.3168

+1%

DSPCLK frequency

150

MHz

Note:

When MCLK1 or MCLK2 is selected as a source for SYSCLK or ASYNCCLK (either directly or via one of the FLLs), the frequency must be

within 1% of the applicable SYSCLK_FREQ or ASYNCCLK_FREQ register setting.

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