CS47L85 datasheet(53/370 Pages) CIRRUS

53 / 370 page

CS47L85

Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R769

(0301h)

Input_Ena

bles_Statu

IN6L_ENA_STS

Input Path 6 (Left) Enable Status

0 = Disabled

1 = Enabled

IN6R_ENA_STS

Input Path 6 (Right) Enable Status

0 = Disabled

1 = Enabled

IN5L_ENA_STS

Input Path 5 (Left) Enable Status

0 = Disabled

1 = Enabled

IN5R_ENA_STS

Input Path 5 (Right) Enable Status

0 = Disabled

1 = Enabled

IN4L_ENA_STS

Input Path 4 (Left) Enable Status

0 = Disabled

1 = Enabled

IN4R_ENA_STS

Input Path 4 (Right) Enable Status

0 = Disabled

1 = Enabled

IN3L_ENA_STS

Input Path 3 (Left) Enable Status

0 = Disabled

1 = Enabled

IN3R_ENA_STS

Input Path 3 (Right) Enable Status

0 = Disabled

1 = Enabled

IN2L_ENA_STS

Input Path 2 (Left) Enable Status

0 = Disabled

1 = Enabled

IN2R_ENA_STS

Input Path 2 (Right) Enable Status

0 = Disabled

1 = Enabled

IN1L_ENA_STS

Input Path 1 (Left) Enable Status

0 = Disabled

1 = Enabled

IN1R_ENA_STS

Input Path 1 (Right) Enable Status

0 = Disabled

1 = Enabled

Table 2 Input Signal Path Enable

INPUT SIGNAL PATH SAMPLE RATE CONTROL

The input signal paths may be selected as input to the digital mixers or signal processing functions within the CS47L85

digital core. The sample rate for the input signal paths is configured using the IN_RATE register - see Table 22 within the

“Digital Core” section.

Note that sample rate conversion is required when routing the input signal paths to any signal chain that is asynchronous

and/or configured for a different sample rate.

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