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CS47L85 bảng dữ liệu(PDF) 115 Page - Cirrus Logic |
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CS47L85 bảng dữ liệu(HTML) 115 Page - Cirrus Logic |
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115 / 370 page ![]() CS47L85 Rev 4.3 115 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3145216 (2FFE00h) DSP5_Co nfig_1 14:11 DSP5_RATE [3:0] 0000 DSP5 Sample Rate 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. All DSP5xMIX_SRCn registers should be set to 00h before changing DSP5_RATE. R3669504 (37FE00h) DSP6_Co nfig_1 14:11 DSP6_RATE [3:0] 0000 DSP6 Sample Rate 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. All DSP6xMIX_SRCn registers should be set to 00h before changing DSP6_RATE. R4193792 (3FFE00h) DSP7_Co nfig_1 14:11 DSP7_RATE [3:0] 0000 DSP7 Sample Rate 0000 = SAMPLE_RATE_1 0001 = SAMPLE_RATE_2 0010 = SAMPLE_RATE_3 1000 = ASYNC_SAMPLE_RATE_1 1001 = ASYNC_SAMPLE_RATE_2 All other codes are Reserved. The selected sample rate is valid in the range 8kHz to 192kHz. All DSP7xMIX_SRCn registers should be set to 00h before changing DSP7_RATE. Table 22 Digital Core Sample Rate Control |
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