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SH79F166AP/044PR bảng dữ liệu(PDF) 84 Page - SINOWEALTH Electronic Ltd |
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SH79F166AP/044PR bảng dữ liệu(HTML) 84 Page - SINOWEALTH Electronic Ltd |
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84 / 113 page  SH79F166A 84 Table 8.22 EUART Data Buffer Register 99H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SBUF SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 SBUF[7:0] This SFR accesses two registers; a transmit shift register and a receive latch register A write of SBUF will send the byte to the transmit shift register and then initiate a transmission A read of SBUF returns the contents of the receive latch Table 8.23 Power Control Register 87H, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PCON SMOD SSTAT - - GF1 GF0 PD IDL R/W R/W R/W - - R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 - - 0 0 0 0 Bit Number Bit Mnemonic Description 7 SMOD Baud rate doubler If set in Mode1 & 3, the baud-rate of EUART is doubled if using time4 as baud-rate generator If set in Mode2, the baud-rate of EUART is doubled 6 SSTAT SCON[7:5] function select bit 0: SCON[7:5] operates as SM0, SM1, SM2 1: SCON[7:5] operates as FE, RXOV, TXCOL 3-2 GF[1:0] General purpose flags for software use 1 PD Power-Down mode control bit 0 IDL Idle mode control bit Table 8.24 EUART Slave Address & Address Mask Register 9AH-9BH, Bank0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SADDR SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR.1 SADDR.0 SADEN SADEN.7 SADEN.6 SADEN.5 SADEN.4 SADEN.3 SADEN.2 SADEN.1 SADEN.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7-0 SADDR[7:0] SFR SADDR defines the EUART’s slave address 7-0 SADEN[7:0] SFR SADEN is a bit mask to determine which bits of SADDR are checked against a received address 0: Corresponding bit in SADDR is a “don’t care” 1: Corresponding bit in SADDR is checked against a received address |
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