SH79F166APSLASH044PR datasheet(35/113 Pages) SINOWEALTH

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SH79F166A

7.7.3 Port Diagram

Data

Data Bus

Write

Read Port Pad

PxCRy

Read Data Register/Pad Selection

Read

PxPCRy

Output Mode

I/O Pad

0: From Pad

1: From data register

SFEN

Second

Function

Input Mode

Read Port Data Register

(Pull-up)

0 = ON

1 = OFF

VDD

0 = OFF

1 = ON

Note:

(1) The input source of reading input port operation is from the input pin directly.

(2) The input source of reading output port operation has two paths, one is from the port data Register, and the other is from the

output pin directly. The read Instruction distinguishes which path is selected: The read-modify-write instruction is for the

reading of the data register in output mode, and the other instructions are for reading of the output pin directly.

(3) The destination of writing port operation is the data register regardless the port shared as the second function or not.

7.7.4 Port Share

The 41 bi-directional I/O ports can also share second or third special function. But the share priority should obey the Outer

Most Inner Lest rule:

The out most pin function in Pin Configuration has the highest priority, and the inner most pin function has the lowest priority.

This means when one pin is occupied by a higher priority function (if enabled), it cannot be used as the lower priority functional

pin, even the lower priority function is also enabled. Only until the higher priority function is closed by hardware or software, can

the corresponding pin be released for the lower priority function use. Also the function that need pull up resister is also

controlled by the same rule.

When port share function is enabled, the user can modify PxCR, PxPCR (x = 0-5), but these operations will have no effect on

the port status until the second function was disabled.

When port share function is enabled, any read or write operation to port will only affect the data register while the port pin keeps

unchanged until all the share functions are disabled.

PORT0:

- LCD Segment 17-19 (P0.0-P0.2)

- PWM01: PWM01 output (P0.2)

- PWM0: PWM0 output (P0.3)

- INT0: external inturrupt0 (P0.4)

- INT1: external inturrupt1 (P0.5)

- INT2: external inturrupt2 (P0.6)

- INT3: external inturrupt3 (P0.7)

- T2: Timer2 external input/baud-rate clock output (P0.5)

- T2EX: Timer2 reload/capture control (P0.4)

- T4: Timer4 external input/baud-rate clock output (P0.3)

- XTALX1: XTAL input (P0.7)

- XTALX2: XTAL output (P0.6)

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