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SH79F166AP/044PR bảng dữ liệu(PDF) 73 Page - SINOWEALTH Electronic Ltd

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SH79F166AP/044PR bảng dữ liệu(HTML) 73 Page - SINOWEALTH Electronic Ltd

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SH79F166A
73
Table 8.16 PWM Period Control Register (PWM0PL)
D3H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PWM0PL
PP0.7
PP0.6
PP0.5
PP0.4
PP0.3
PP0.2
PP0.1
PP0.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
(POR/WDT/LVR/PIN)
0
0
0
0
0
0
0
0
Bit Number
Bit Mnemonic
Description
7-0
PP0[7:0]
12-bit PWM period low 8 nibble registers
Table 8.17 PWM Period Control Register (PWM0PH)
D4H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PWM0PH
-
-
-
-
PP0.11
PP0.10
PP0.9
PP0.8
R/W
-
-
-
-
R/W
R/W
R/W
R/W
Reset Value
(POR/WDT/LVR/PIN)
-
-
-
-
0
0
0
0
Bit Number
Bit Mnemonic
Description
3-0
PP0[11:8]
12-bit PWM period high 4 nibble registers
PWM output period cycle = [PP0.11, PP0.0] X PWM clock.
When [PP0.11, PP0.0] = 000H, PWM0 outputs GND if the PWM0S bit is set to “0” regardless of PWM duty cycle.
When [PP0.11, PP0.0] = 000H, PWM0 outputs high level if the PWM0S bit is set to “1” regardless of PWM duty cycle.
Table 8.18 PWM Duty Control Register (PWM0DL)
D5H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PWM0DL
PD0.7
PD0.6
PD0.5
PD0.4
PD0.3
PD0.2
PD0.1
PD0.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
(POR/WDT/LVR/PIN)
0
0
0
0
0
0
0
0
Bit Number
Bit Mnemonic
Description
7-0
PD0[7:0]
12-bit PWM duty low 8 nibble registers
Table 8.19 PWM Duty Control Register (PWM0DH)
D6H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PWM0DH
-
-
-
-
PD0.11
PD0.10
PD0.9
PD0.8
R/W
-
-
-
-
R/W
R/W
R/W
R/W
Reset Value
(POR/WDT/LVR/PIN)
-
-
-
-
0
0
0
0
Bit Number
Bit Mnemonic
Description
3-0
PD0[11:8]
12-bit PWM duty high 4 nibble registers
PWM output duty cycle = [PD0.11, PD0.0] X PWM clock.
If [PP0.11, PP0.0]
≤ [PD0.11, PD0.0], PWM0 outputs high level when the PWM0S bit is set to “0”.
If [PP0.11, PP0.0]
≤ [PD0.11, PD0.0], PWM0 outputs GND level when the PWM0S bit is set to “1”.



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