R7FA6T2AB3CFP datasheet(51/93 Pages) RENESAS

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Table 2.28

SPI timing (2 of 2)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

High Speed/

Default

Symbol

VCC = 3.0 to 3.6 V, C = 15

VCC = 2.7 to 3.6 V, C = 30

Unit

Note

Min

Max

Min

Max

Data output delay

time

Master　 High

Speed*1

tOD　　　

—

4.6

—

Default*2

—

Slave　

High

Speed*1

—

Default*2

—

Data output hold

time

Master

tOH

—

Slave

—

Successive

transmission delay

time

Master

tTD

tSPcyc + 2 ×

tTcyc

8 × tSPcyc +

2 × tPcyc

tSPcyc + 2 ×

tTcyc

8 × tSPcyc +

2 × tPcyc

Slave

tTcyc

—

tTcyc

—

MOSI and MISO

rise and fall time

Output

tDr

—

Input

tDf

—

µs

SSL rise and fall

time

Output

tSSLr

—

Input

tSSLf

—

µs

Slave access time

Slave

tSA

—

Slave output

release time

Slave

tREL

—

Note:

tTcyc: PCLKA or SCISPICLK cycle.

Note 1. Must use pins that have a letter appended to their name, for instance _A, _B, _C, to indicate group membership. SPIA is instance

_B, SPIB is instance _A.

Note 2. All pins of group membership can be used.

RSPCKn

master select

output

RSPCKn

slave select input

tSPCKWH

VOH

VOL

VOH

tSPCKWL

tSPCKr

tSPCKf

VOL

tSPcyc

tSPCKWH

VIH

VIL

VIH

tSPCKWL

tSPCKr

tSPCKf

VIL

tSPcyc

VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC

Note:

n = A or B

Figure 2.39

SPI clock timing

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0120 Rev.1.20

Mar 31, 2022

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