R7FA6T2AB3CFP datasheet(45/93 Pages) RENESAS

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Table 2.24

SCI timing (Simple SPI) (2 of 2)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

High Speed/

Default

Symbol

Min

Max

Unit

Note

SCK clock high pulse width

Master

tSPCKWH

0.4

0.6

tSPcyc

Slave

SCK clock low pulse width

Master

tSPCKWL

0.4

0.6

tSPcyc

Slave

SCK clock rise and fall time

Output

tSPCKr, tSPCKf

—

Input

—

Data input setup time　

Master

High Speed*1

tSU

1.7

—

Default*2

—

Slave

3.3

—

Data input hold time

Master

High Speed*1

—

Default*2

—

Slave

—

Data output delay

Master

High Speed*1

tOD

—

Default*2

—

7.3

Slave

High Speed*1

—

Default*2

—

Data output hold time

Master

tOH

—

Slave

—

Data rise and fall time

Output

tDr, tDf

—

Input

—

Slave access time

tSA

—

tTcyc

Slave output release time

tREL

—

tTcyc

Note:

tTcyc: SCITCLK cycle.

Note 1. Must use pins that have a letter appended to their name, for instance _A, _B, _C, to indicate group membership. SCI0 is instance

_A, SCI2 and SCI3 are instance _B, SCI1 and SCI9 are instance _C, SCI4 is instance _C and RXD is only PD14.

Note 2. All pins of group membership can be used.

Table 2.25

SCI timing (Simple SPI mode)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Note

SS input setup time

tLEAD

—

tSPcyc

SS input hold time

tLAG

—

tSPcyc

SS input rise and fall time

tSSLr, tSSLf

—

Table 2.26

SCI timing (Clock synchronous mode) (1 of 2)

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

High Speed/

Default

Symbol

Min

Max

Unit

Note

SCK clock cycle output

Master

tSPcyc

—

tTcyc

SCK clock cycle input

Slave

—

SCK clock high pulse width

Master

tSPCKWH

0.4

0.6

tSPcyc

Slave

RA6T2 Datasheet

2. Electrical Characteristics

R01DS0400EJ0120 Rev.1.20

Mar 31, 2022

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