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Table 1.3

System (2 of 2)

Feature

Functional description

Clock Frequency Accuracy

Measurement Circuit (CAC)

The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be

measured (measurement target clock) within the time generated by the clock selected as the

measurement reference (measurement reference clock), and determines the accuracy

depending on whether the number of pulses is within the allowable range.When measurement is

complete or the number of pulses within the time generated by the measurement reference clock

is not within the allowable range, an interrupt request is generated.

Interrupt Controller Unit (ICU)

The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector

Interrupt Controller (NVIC), the DMA Controller (DMAC), and the Data Transfer Controller (DTC)

modules. The ICU also controls non-maskable interrupts.

Key Interrupt Function (KINT)

The key interrupt function (KINT) generates the key interrupt by detecting rising or falling edge

on the key interrupt input pins.

Low power modes

Power consumption can be reduced in multiple ways, including setting clock dividers, stopping

modules, selecting power control mode in normal operation, and transitioning to low power

modes.

The register write protection function protects important registers from being overwritten due to

software errors. The registers to be protected are set with the Protect Register (PRCR).

Memory Protection Unit (MPU)

The MCU has one Memory Protection Unit (MPU).

Table 1.4

Event link

Feature

Functional description

Event Link Controller (ELC)

The Event Link Controller (ELC) uses the event requests generated by various peripheral

modules as source signals to connect them to different modules, allowing direct link between the

modules without CPU intervention.

Table 1.5

Direct memory access

Feature

Functional description

Data Transfer Controller (DTC)

A Data Transfer Controller (DTC) module is provided for transferring data when activated by an

interrupt request.

DMA Controller (DMAC)

The MCU includes an 8-channel direct memory access controller (DMAC) that can transfer data

without intervention from the CPU. When a DMA transfer request is generated, the DMAC

transfers data stored at the transfer source address to the transfer destination address.

Table 1.6

Timers (1 of 2)

Feature

Functional description

General PWM Timer (GPT)

The General PWM Timer (GPT) is a 32-bit timer with GPT32 × 10 channels. PWM waveforms

can be generated by controlling the up-counter, down-counter, or the up- and down-counter. In

addition, PWM waveforms can be generated for controlling brushless DC motors. The GPT can

also be used as a general-purpose timer.

PWM Delay Generation Circuit (PDG)

The PWM Delay Generation circuit (PDG) has 4 channels delay circuits that can connect to the

GPT. The PDG can control the rise and fall edge timing with which the PWM output for the

GPT320 through the GPT323.

Port Output Enable for GPT (POEG)

The POEG issues requests to stop output from output pins of the general PWM timer (GPT).

Select the method of detection for stopping the output from the list below.

Low power Asynchronous General

Purpose Timer (AGT)

The low power Asynchronous General Purpose Timer (AGT) is a 32-bit timer that can be used

for pulse output, external pulse width or period measurement, and counting external events. This

timer consists of a reload register and a down counter. The reload register and the down counter

are allocated to the same address, and can be accessed with the AGT register.

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a 14-bit down counter that can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, the WDT can be used to generate a non-maskable interrupt or an underflow

interrupt.

RA6T2 Datasheet

1. Overview

R01DS0400EJ0120 Rev.1.20

Mar 31, 2022

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