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R7FA6T2AB3CFP bảng dữ liệu(PDF) 37 Page - Renesas Technology Corp

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Table 2.20
I/O ports, POEG, GPT, AGT, KINT and ADC trigger timing (2 of 4)
GPT Conditions:
High drive output is selected in the Port Drive Capability bit in the PmnPFS register.
AGT Conditions:
Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
POEG
GTETRGn input pulse width
tPOEW
1.5
—
—
tPcyc
Figure 2.15
Output
disable time
Input level detection of the
GTETRGn pin (via flag)
tPOEGDI
—
—
3 PCLKB
+ 0.34
µs
Figure 2.16
When the digital
noise filter is not
in use
(POEGGn.NFE
N = 0 (n = A to
D))
Detection of the output stopping
signal from GPT (deadtime error,
simultaneous high output, or
simultaneous low output)
tPOEGDE
—
—
0.5
µs
Figure 2.17
Edge detection signal from a
comparator
tPOEGDC
—
—
4 PCLKB
+ 0.5
µs
Figure 2.18
The time is that
when the noise
filter for
ACMPHS is not
in use
(CMPCTL.CDF
S[1:0] = 00) and
excludes the
time for
detection by
ACMPHS.
Register setting
tPOEGDS
—
—
1 PCLKB
+ 0.3
µs
Figure 2.19
Time for access
to the register is
not included.
Oscillation stop detection*3
tPOEGDOS —
≤ 1
—
µs
Figure 2.20
Input level detection of the
GTETRGn pin (direct path)
tPOEGDDI —
—
2 PCLKB
+ 1
PCLKD +
0.34
µs
Figure 2.21
Level detection signal from a
comparator
tPOEGDDC —
—
3 PCLKD
+ 0.3
µs
Figure 2.22
The time is that
when the noise
filter for
ACMPHS is not
in use
(CMPCTL.CDF
S[1:0] = 00) and
excludes the
time for
detection by
ACMPHS.
RA6T2 Datasheet
2. Electrical Characteristics
R01DS0400EJ0120 Rev.1.20
Mar 31, 2022
Page 37 of 93



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