MPC5675KFF0VMS2R datasheet(90/147 Pages) NXP

90 / 147 page

MPC5675K Microcontroller Data Sheet, Rev. 9

Electrical characteristics

NXP Semiconductors

3.18

PDI pads specifications

This section specifies the electrical characteristics of the PDI pads. Please refer to the tables in Section 2.2, Pin descriptions, for

a cross reference between package pins and pad types.

PDI pads feature list:

•

Direction

— Input

— Output

— Bidirectional

•

Driver

— Push/Pull/Open Drain

— Configurable Four Drive Strengths on Fast driver pads

— Configurable No Slew-Rate, Slow Slew-Rate, and Fast Slew-Rate on Slow, Medium, and SLR driver pads

— VDD_HV_PDI NOTE: All pads are NOT 5 V TOLERANT. Pads are not capable of driving to or from voltages

above their respective VDD_HV_PDI. In other words, you cannot connect a 3.3V external device to a pad

supplied with 2.5 V. If a pad must be connected to a 3.3V device, its local VDD_HV_PDI must be 3.3 V. Injection

current is then handled by the intrinsic diodes from the pad transistors and by the ESD diodes.

— VDD_HV_PDI range 1.8 V to 3.3 V, as specified in the following tables

•

Receiver

— Selectable hysteresis input buffer

—CMOS Input Buffer

The electrical data provided in this section applies:

•

To the pads listed in Table 37

•

Over the voltage range 1.62–3.6 V

High

Normal Operation

Table 37. PDI I/O pads

No.

Name

Voltage

Used for

Notes

PDI Fast

1.62–3.6 V

I/O

Enhanced operating voltage range fast slew-rate output with four selectable

slew-rates. Contains an input buffer and weak pullup/pulldown.

2PDI

Medium

Enhanced operating voltage range medium slew-rate output with four

selectable slew-rates. Contains an input buffer and weak pullup/pulldown.

Table 38. PDI pads DC electrical characteristics1

No.

Symbol

Parameter

Min

Max

Unit

1VDD_HV_PDI SR I/O supply voltage

1.62

3.6

2VIH_C

CC CMOS input buffer high voltage

(hysteresis enabled)

0.65 × VDD_HV_PDI VDD_HV_PDI +0.3

3VIH_C

CC CMOS input buffer high voltage

(hysteresis disabled)

0.58 × VDD_HV_PDI VDD_HV_PDI +0.3

Table 36. Power sequence pin states for GPIO pads

VDD_LV_COR

VDD_HV_IO

Pad Function

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