MPC5675KFF0VMS2R datasheet(8/147 Pages) NXP

8 / 147 page

MPC5675K Microcontroller Data Sheet, Rev. 9

Introduction

NXP Semiconductors

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16-region MPU with concurrent checks against each master access

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32-byte granularity for protected address region

1.6.4

Enhanced Direct Memory Access (eDMA) controller

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32 channels support independent 8-, 16-, 32-bit single value or block transfers

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Supports variable-sized queues and circular queues

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Source and destination address registers are independently configured to post-increment or remain constant

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Each transfer is initiated by a peripheral, CPU, or eDMA channel request

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Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block

transfer

1.6.5

Interrupt Controller (INTC)

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208 peripheral interrupt requests

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8 software settable sources

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Unique 9-bit vector per interrupt source

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16 priority levels with fixed hardware arbitration within priority levels for each interrupt source

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Priority elevation for shared resources

1.6.6

Frequency-Modulated Phase-Locked Loop (FMPLL)

Two FMPLLs are available on each device.

Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock.

Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor and

output clock divider ratio are software configurable. The FMPLLs have the following major features:

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Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator)

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Voltage controlled oscillator (VCO) range: 256–512 MHz

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Frequency modulation via software control to reduce and control emission peaks

— Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register

— Modulation frequency: triangular modulation with 25 kHz nominal rate

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Option to switch modulation on and off via software interface

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Reduced frequency divider (RFD) for reduced frequency operation without re-lock

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2 modes of operation

— Normal PLL mode with crystal reference (default)

— Normal PLL mode with external reference

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Lock monitor circuitry with lock status

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Loss-of-lock detection for reference and feedback clocks

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Self-clocked mode (SCM) operation

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Auxiliary FMPLL

— Used for FlexRay due to precise symbol rate requirement by the protocol

— Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies

of operation for PWM and timers as well as jitter-free control

— Option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in

electric motor control loop

— Allows running motor control periphery at different (precisely lower, equal, or higher, as required) frequency than

the system to ensure higher resolution

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