MPC5675KFF0VMS2R datasheet(79/147 Pages) NXP

79 / 147 page

Electrical characteristics

MPC5675K Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

3.13

16 MHz RC oscillator electrical characteristics

Δt

LTJIT

T Long term jitter

PHI @ 16 MHz,

Input clock @ 4 MHz

——

±6

fLCK

D Frequency LOCK range

—

–4

—

fFMPLLOUT

fUL

D Frequency un-LOCK range

—

–16

—

+16

fFMPLLOUT

17a

fCS

fDS

D Modulation Depth

Center spread

±0.25

—

±4

fFMPLLOUT

17b

Down Spread

–0.5

—

–8

fMOD

D Modulation frequency13

31 < LDF14 <63

LDF > 63

—

(2240/LD

kHz

1 Considering operation with FMPLL not bypassed.

2 PFD clock range is 4– 16 MHz. An appropriate PLL Input division factor (IDF) should be chosen to divide the reference

frequency to this range.

3 “Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self clocked mode.

4 Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls outside the f

LOR

window.

5 f

VCO is the frequency at the output of the VCO; its range is 256–512 MHz.

fSCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz.

fsys =fVCO÷ODF

6 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this

FMPLL, load capacitors should not exceed these limits.

7 This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR).

8 This value is determined by the crystal manufacturer and board design.

9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

FMPLLOUT.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER

percentage for a given interval.

10 Proper PC board layout procedures must be followed to achieve specifications.

11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C

JITTER and either fCS

or fDS (depending on whether center spread or down spread modulation is enabled).

12 Core operating at 180 MHz.

13 Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz.

14 PLL Loop Division Factor (LDF).

Table 23. RC oscillator electrical characteristics

No.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

1fRC

CC RC oscillator frequency

25 °C, 1.2 V trimmed

—

MHz

RCMVAR

CC Frequency spread: The variation in

output frequency from PTF1 across

temperature and supply voltage range

——

—

±5

Table 22. FMPLL electrical characteristics (continued)

No.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

MPC5675KFF0VMS2R bảng dữ liệu(PDF) 79 Page - NXP Semiconductors

MPC5675KFF0VMS2R bảng dữ liệu(HTML) 79 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL