38B5 datasheet(17/70 Pages) RENESAS

17 / 70 page

MITSUBISHI MICROCOMPUTERS

38B5 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

Interrupts

Interrupts occur by twenty one sources: five external, fifteen internal,

and one software.

(1) Interrupt Control

Each interrupt except the BRK instruction interrupt have both an

interrupt request bit and an interrupt enable bit, and is controlled by

the interrupt disable flag. An interrupt occurs if the corresponding

interrupt request and enable bits are “1” and the interrupt disable flag

is “0.” Interrupt enable bits can be set or cleared by software. Inter-

rupt request bits can be cleared by software, but cannot be set by

software. The BRK instruction interrupt and reset cannot be disabled

with any flag or bit. The I flag disables all interrupts except the BRK

instruction interrupt and reset. If several interrupts requests occurs

at the same time the interrupt with highest priority is accepted first.

(2) Interrupt Operation

Upon acceptance of an interrupt the following operations are auto-

matically performed:

1. The contents of the program counter and processor status

2. The interrupt disable flag is set and the corresponding

interrupt request bit is cleared.

3. The interrupt jump destination address is read from the vector

table into the program counter.

sNotes on Use

When the active edge of an external interrupt (INT0–INT4) is set or

when switching interrupt sources in the same vector address, the

corresponding interrupt request bit may also be set. Therefore, please

take following sequence:

(1) Disable the external interrupt which is selected.

(2) Change the active edge in interrupt edge selection register

(3) Clear the set interrupt request bit to “0.”

(4) Enable the external interrupt which is selected.

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