38B5 datasheet(38/70 Pages) RENESAS

38 / 70 page

MITSUBISHI MICROCOMPUTERS

38B5 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

[FLDC Mode Register] FLDM

The FLDC mode register is a 8-bit register respectively which is used

to control the FLD automatic display and to set the blanking time

Tscan for key-scan.

Fig. 40 Structure of FLDC Mode Register

FLDC mode register

(FLDM: address 0EF416)

Automatic display control bit (P0, P1, P2, P3, P8)

0 : General-purpose mode

1 : Automatic display mode

Display start bit

0 : Stop display

1 : Display

(start to display by switching “0” to “1”)

Tscan control bits

00 : FLD digit interrupt (at rising edge of each digit)

01 : 1 ! Tdisp

10 : 2 ! Tdisp

11 : 3 ! Tdisp

Timing number control bit

0 : 16 timing mode

1 : 32 timing mode

Gradation display mode selection control bit

0 : Not selecting

1 : Selecting (Note)

Tdisp counter count source selection bit

0 : f(XIN)/16 or f(XCIN)/32

1 : f(XIN)/64 or f(XCIN)/128

High-breakdown voltage port drivability selection bit

0 : Drivability strong

1 : Drivability weak

FLD blanking interrupt

(at falling edge of the last digit)

Note: When a gradation display mode is selected, a number of timing is max. 16 timing.

(Set the timing number control bit to “0.”)

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