38B5 datasheet(40/70 Pages) RENESAS

40 / 70 page

MITSUBISHI MICROCOMPUTERS

38B5 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

FLD automatic display RAM

The FLD automatic display RAM uses the 160 bytes of addresses

0F6016 to 0FFF16. For FLD, the 3 modes of 16-timing ordinary mode,

16-timing•gradation display mode and 32-timing mode are available

depending on the number of timings and the presence/absence of

gradation display.

The automatic display RAM in each mode is as follows:

(1) 16-timing•Ordinary Mode

The 80 bytes of addresses 0FB016 to 0FFF16 are used as a FLD

display data store area. Because addresses 0F6016 to 0FAF16

are not used as the automatic display RAM, they can be the ordi-

nary RAM or serial I/O automatic reverse RAM.

(2) 16-timing•Gradation Display Mode

The 160 bytes of addresses 0F6016 to 0FFF16 are used. The 80

bytes of addresses 0FB016 to 0FFF16 are used as an FLD dis-

play data store area, while the 80 bytes of addresses 0F6016 to

0FAF16 are used as a gradation display control data store area.

(3) 32-timing Mode

The 160 bytes of addresses 0F6016 to 0FFF16 are used as an

FLD display data store area.

[FLD Data Pointer and FLD Data Pointer Reload Register]

FLDDP (0EF816)

Both the FLD data pointer and FLD data pointer reload register are

8-bit registers assigned at address 0EF816. When writing data to this

address, the data is written to the FLD data pointer reload register;

when reading data from this address, the value in the FLD data pointer

is read.

Fig. 42 FLD Automatic Display RAM Assignment

16-timing•ordinary mode

0FFF16

0FB016

0F6016

0FFF16

0F6016

0FFF16

0FB016

0F6016

16-timing•gradation display mode

32-timing mode

1 to 32 timing display

data stored area

Gradation display

control data stored

area

1 to 16 timing display

data stored area

1 to 16 timing display

data stored area

Not used

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