38B5 datasheet(51/70 Pages) RENESAS

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MITSUBISHI MICROCOMPUTERS

38B5 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

PRELIMINAR

Notice:

This

is not

a final

specification.

Some

parametric

limits

are

subject

to change.

Fig. 56 14-bit PWM Timing

Fig. 55 Structure of PWM Control Register

P87/PWM output selection bit

0: I/O port

1: PWM output

Not used (return “0” when read)

PWM control register

(PWMCON: address 002616)

ADD

165316

1A9316

1AA416

1EE416

1EF516

T = 4096

µs

t = 64

µs

1316

A416

2416

3516

7B16

6A16

5916

Data 3516 stored at address 001516

t = 64

µs

τ = 0.25 µs

“H” period length specified by PWMH

B516

PWM register

(high-order)

PWM register

(low-order)

PWM latch

(14-bit)

Data 6A16 stored at address 001416

Data 2416 stored at address 001516

Bit 7 cleared after transfer

Transfer from register to latch

Data 7B16 stored at address 001416

Transfer from register to latch

When bit 7 of PWML is “0,” transfer

from register to latch is disabled.

PWM output

(Example 1)

Low-order 6-bits

output

H = 6A16

L = 2416

6B16............36 times

(107)

6A16............28 times

(106)

PWM output

(Example 2)

Low-order 6 bits

output

H = 6A16

L = 1816

6B16............24 times

6A16............40 times

PWM output

8-bit counter

The ADD portions with

additional

τ are determined

either “H” or “L” by low-order

6-bit data.

Minimum bit width

(64

µs)

106 ! 64 + 24

(256

0.25

µs)

256

(64

µs), fixed

106 ! 64 + 36

………

.............

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