AT25QL641 datasheet(37/77 Pages) DIALOG

tên linh kiện	AT25QL641

Giải thích chi tiết về linh kiện	64-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

PDF	77 Pages

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AT25QL641

DS-25QL641–130E–10/2018

Figure 7-31. 64KB Block Erase Instruction (QPI Mode)

7.20

Chip Erase (C7h / 60h)

The ‘Chip Erase’ instruction sets all bits in the memory to 1. Prior to the ‘Chip Erase’ instruction, a ‘Write Enable’ (06h)

instruction must be issued. The instruction is initiated by driving the CS pin low and shifting the instruction code “C7h” or

“60h”. Refer to Figure 7-32 below. The CS pin must go high after the eighth bit of the last byte has been latched in,

otherwise, the Chip Erase instruction is not executed. After CS is driven high, the self-timed Chip Erase instruction

commences for a duration of t

CE (see Table 8-7, AC Electrical Characteristics).

While the chip erase operation is in progress, the ‘Read Status Register’ (05h) instruction may still be accessed to check

the status of the BUSY bit. The BUSY bit is a 1 during the chip erase operation and becomes a 0 when the cycle is

finished and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable

Latch (WEL) bit in the Status Register is cleared to 0.

Figure 7-32. Chip Erase Instruction for SPI Mode (left) and QPI Mode (right)

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