AT25QL641 datasheet(20/77 Pages) DIALOG

tên linh kiện	AT25QL641

Giải thích chi tiết về linh kiện	64-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

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AT25QL641

DS-25QL641–130E–10/2018

Enable for Volatile Status Register (50h) is set in QPI Mode, the SUS bit (S15) and Reserved bits (S13, S12, S11 and

S10) of Status Register-2 must be driven to high after Write Status Register instruction (01h). Once Read Status Register

(05h or 35h) is issued the read values of SUS bit (S15) and Reserved bits (S13, S12, S11 and S10) of the Status

Figure 7-2.

Write Enable for Volatile Status Register Instruction for SPI Mode (left) and QPI Mode (right)

7.4

Write Disable (04h)

The Write Disable instruction is used to reset the Write Enable Latch (WEL) bit in the Status Register. To enter the Write

Disable instruction, CS goes low prior to the instruction “04h” into Data Input (SI) pin on the rising edge of SCK, and then

driving CS high. T h e WEL bit is automatically reset write- disable status of “0” after power-up and upon completion of the

every Program, Erase and Write Status Register instructions.

Figure 7-3.

Write Disable Instruction for SPI Mode (left) and QPI Mode (right)

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