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AT25QL641 bảng dữ liệu(PDF) 69 Page - Dialog Semiconductor |
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AT25QL641 bảng dữ liệu(HTML) 69 Page - Dialog Semiconductor |
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69 / 77 page ![]() 68 AT25QL641 DS-25QL641–130E–10/2018 8.3 AC Electrical Characteristics Table 8-7. AC Electrical Characteristics Parameter (1) Symbol Alt Min Typ Max Unit Clock frequency for all instructions, except Read Data and Fast Read Data in SPI mode (03h, 0Bh) 1.7V - 2.0V VCC and industrial temperature fR fc D.C. 133 MHz Clock freq. Fast Read Data instruction in SPI mode (0Bh) fR D.C. 104 MHz Clock freq. Read Data instruction in SPI mode (03h) fR D.C. 50 MHz Clock High, Low Time except Read Data (03h) t CLH, tCLL (2) 3.5 ns Clock High, Low Time for Read Data (03h) t CRLH, tCRLL (2) 8 ns Clock Rise Time peak-to-peak t CLCH (3) 0.1 V/ns Clock Fall Time peak-to-peak t CHCL (3) 0.1 V/ns CS Active Setup Time relative to Clock t SLCH t CSS 5 ns CS Not Active Hold Time relative to Clock tCHSL 5 ns Data In Setup Time t DVCH t DSU 2 ns Data In Hold Time t CHDX t DH 3 ns CS Active Hold Time relative to Clock t CHSH 5 ns CS Not Active Setup Time relative to Clock t CHSH 5 ns CS Deselect Time (for Read instructions/Write, Erase and Program instructions) t SHSL t CSH 100 ns Output Disable Time t SHQZ(3) t DIS 7 ns Clock Low to Output Valid tCLQV tV1 6 ns Clock Low to Output Valid (Except Main Read) (4) tCLQV tV2 7 ns Output Hold Time tCLQX tHO 1.5 ns HOLD Active Setup Time relative to Clock t HLCH 5 ns HOLD Active Hold Time relative to Clock t CHHH 5 ns HOLD Not Active Setup Time relative to Clock t HHCH 5 ns HOLD Not Active Hold Time relative to Clock t CHHL 5 ns HOLD to Output Low-Z t HHQX (3) tLZ 7 ns HOLD to Output High-Z t HLQZ (3) tHZ 12 ns Write Protect Setup Time Before CS Low t WHSL (5) 20 ns Write Protect Setup Time After CS High tSHWL (5) 100 ns CS High to Power Down Mode t DP (3) 3 µs CS High to Standby Mode without Electronic Signature Read t RES1 (3) 3 µs CS High to Standby Mode with Electronic Signature Read t RES2 (3) 1.8 µs |
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